View AD7190_8444012.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

4.8 khz ultralow noise 24-bit sigma-delta adc with pga data sheet AD7190 rev. c document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2008C2013 analog devices, inc. all rights reserved. technical support www.analog.com features rms noise: 8.5 nv @ 4.7 hz (gain = 128) 16 noise free bits @ 2.4 khz (gain = 128) up to 22.5 noise free bits (gain = 1) offset drift: 5 nv/c gain drift: 1 ppm/c specified drift over time 2 differential/4 pseudo differential input channels automatic channel sequencer programmable gain (1 to 128) output data rate: 4.7 hz to 4.8 khz internal or external clock simultaneous 50 hz/60 hz rejection 4 general-purpose digital outputs power supply av dd : 4.75 v to 5.25 v dv dd : 2.7 v to 5.25 v current: 6 ma temperature range: C40c to +105c interface 3-wire serial spi, qspi?, microwire?, and dsp compatible schmitt trigger on sclk qualified for automotive applications applications weigh scales strain gauge transducers pressure measurement temperature measurement chromatography plc/dcs analog input modules data acquisition medical and scientific instrumentation general description the AD7190 is a low noise, complete analog front end for high precision measurement applications. it contains a low noise, 24-bit sigma-delta (-) analog-t o-digital converter (adc). the on-chip low noise gain stage means that signals of small amplitude can be interfaced directly to the adc. the device can be configured to have two differential inputs or four pseudo differential inputs . the on-chip channel sequencer allows several channels to be enabled, and the AD7190 sequentially converts on each en abled channel. this simplifies communication with the part. the on-chip 4.92 mhz clock can be used as the clock source to the adc or, alternatively, an external clock or crystal can be used. the output data rate from the part can be varied from 4.7 hz to 4.8 khz. the device has two digital filter options. the choice of filter affects the rms noise/noise-free resolution at the programmed output data rate, the settling time, and the 50 hz/60 hz rejection. for applications that require all conversions to be settled, the AD7190 includes a zero latency feature. the part operates with 5 v analog power supply and a digital power supply from 2.7 v to 5.25 v. it consumes a current of 6 ma. it is housed in a 24-lead tssop package. functional block diagram mclk1 mclk2 p0/refin2(?) p1/refin2(+) dv dd dgnd refin1(+) refin1(?) ain1 ain2 ain3 ain4 a incom bpdsw agnd AD7190 reference detect serial interface and control logic temp sensor clock circuitry dout/rdy din sclk cs sync p3 p2 av dd agnd - ? adc pga mux 07640-001 figure 1.
important links for the AD7190 * last content update 12/19/2013 06:54 pm similar products & parametric selection tables find similar products by operating parameters suggested companion products recommended precision references for the AD7190 for low noise and low power applications, we recommend the adr421 . for high current output applications, try the adr431 . for additional precision reference selections, we recommend filtering on our our parametric search tables. recommended precision driver amplifiers for the AD7190 for low noise and low power applications, we recommend the ada4051-2 . for more precision and great temperature dirft specs, we recommend the ad8539 . for higher supply voltages up to +-8v, we recommend the ad8639 . for additional precision amplifier selections, we recommend selecting the product category and filtering on our parametric search tables. recommended digital isolators for the AD7190 for isolated data and power, we recommend the adum3470 family in various channel configurations. for additional digital isolator selections, we recommend filtering on our parametric search tables. recommended linear regulators for the AD7190 for powering the separate avdd and dvdd supplies, we recommend the adp3303 . documentation an-1131: chopping on the AD7190, ad7192, ad7193, ad7194, and ad719 an-1084: channel switching: AD7190, ad7192, ad7193, ad7194, ad7195 an-1069: zero latency for the AD7190, ad7192, ad7193, ad7194, and ad7195 an-0979: digital filtering options: AD7190, ad7192 cn-0102: precision weigh scale design using the AD7190 24-bit sigma-delta adc with internal pga AD7190 active functional adc model tutorial on technical and performance benefits of ad719x family ug-222: evaluation board for the AD7190/ad7192 4.8 khz ultralow noise 24-bit sigma-delta adcs ms-2210: designing power supplies for high speed adc view the AD7190 product page for more documentation faqs for the ad719x family. design tools, models, drivers & software download the AD7190 active functional model digital filter model spreadsheets AD7190 - microcontroller no-os driver ad7192 iio high precision adc linux driver (wiki site) evaluation kits & symbols & footprints view the evaluation boards and kits page for documentation and purchasing symbols and footprints design collaboration community collaborate online with the adi support team and other designers about select adi products. follow us on twitter: www.twitter.com/adi_news like us on facebook: www.facebook.com/analogdevicesinc design support submit your support request here: linear and data converters embedded processing and dsp telephone our customer interaction centers toll free: americas: 1-800-262-5643 europe: 00800-266-822-82 china: 4006-100-006 india: 1800-419-0108 russia: 8-800-555-45-90 quality and reliability lead(pb)-free data sample & buy AD7190 view price & packaging request evaluation board request samples check inventory & purchase find local distributors * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page (labeled 'important links') does not constitute a change to the revision number of the product data sheet. this content may be frequently modified. powered by tcpdf (www.tcpdf.org)
AD7190 data sheet rev. c | page 2 of 40 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing characteristics ................................................................ 7 circuit and timing diagrams ..................................................... 7 absolute maximum ratings ............................................................ 9 thermal resistance ...................................................................... 9 esd caution .................................................................................. 9 pin configuration and function descriptions ........................... 10 typical performance characteristics ........................................... 12 rms noise and resolution ............................................................ 15 sinc 4 chop disabled ................................................................... 15 sinc 3 chop disabled ................................................................... 16 sinc 4 chop enabled .................................................................... 17 sinc 3 chop enabled .................................................................... 18 on-chip registers .......................................................................... 19 communications register ......................................................... 19 status register ............................................................................. 20 mode register ............................................................................. 20 configuration register .............................................................. 22 data register ............................................................................... 24 id register ................................................................................... 24 gpocon register ..................................................................... 24 offset register ............................................................................. 25 full-scale register ...................................................................... 25 adc circuit information .............................................................. 26 overview ..................................................................................... 26 filter, output data rate, settling time ................................... 26 digital interface .......................................................................... 29 circuit description......................................................................... 33 analog input channel ............................................................... 33 pga .............................................................................................. 33 bipolar/unipolar configuration .............................................. 33 data output coding .................................................................. 33 clock ............................................................................................ 33 burnout currents ....................................................................... 34 reference ..................................................................................... 34 reference detect ......................................................................... 34 reset ............................................................................................. 34 system synchronization ............................................................ 35 temperature sensor ................................................................... 35 bridge power-down switch ...................................................... 35 logic outputs ............................................................................. 35 enable parity ............................................................................... 36 calibration ................................................................................... 36 grounding and layout .............................................................. 37 applications information .............................................................. 38 weigh scales ................................................................................ 38 outline dimensions ....................................................................... 39 ordering guide .......................................................................... 39 automotive products ................................................................. 39 revision history 2/13rev. b to rev. c added automotive inform ation (throughout) ........................... 1 added automotive specifications, table 1 .................................... 3 changes to ordering guide .......................................................... 39 5/09rev. a to rev. b changes to table 3 ............................................................................ 9 5/09rev. 0 to rev. a changes to table 1 ............................................................................ 3 changes to table 3 and table 4 ....................................................... 9 changes to table 5 .......................................................................... 10 changes to table 6 and table 7 ..................................................... 15 changes to status register section .............................................. 20 changes to table 17 ........................................................................ 21 changes to table 19 ........................................................................ 23 changes to table 20 ....................................................................... 24 added id register section ............................................................ 24 changes to table 21 ....................................................................... 25 changes to filter, output data rate, settling time section .... 26 changes to continuous conversion mode section ................... 31 changes to analog input channel and bipolar/unipolar configuration sections .................................................................. 33 changes to burnout currents, reference, reference detect, and reset sections .................................................................................. 34 changes to temperature sensor section ..................................... 35 changes to calibration section .................................................... 36 changes to grounding and layout section ................................ 37 changes to weigh scales section ................................................. 38 changes to ordering guide .......................................................... 39 10/08revision 0initial version
data sheet AD7190 rev. c | page 3 of 40 specifications av dd = 4.75 v to 5.25 v, dv dd = 2.7 v to 5.25 v, agnd = dgnd = 0 v, refinx(+) = av dd , refinx(?) = agnd, mclk = 4.92 mhz, t a = t min to t max , unless otherwise noted. table 1. parameter AD7190b unit test conditions/comments 1 adc output data rate 4.7 to 4800 hz nom chop disabled. 1.17 to 1200 hz nom chop enabled, sinc 4 filter. 1.56 to 1600 hz nom chop enabled, sinc 3 filter. no missing codes 2 24 bits min fs > 1, sinc 4 filter 3 . 24 bits min fs > 4, sinc 3 filter 3 . resolution see the rms noise and resolution section rms noise and output data rates see the rms noise and resolution section integral nonlinearity b grade 5 ppm of fsr max 1 ppm typical, gain = 1. 15 ppm of fsr max 5 ppm typical, gain > 1. wb grade 7 ppm of fsr max 1 ppm typical, gain = 1. 30 ppm of fsr max 5 ppm typical, gain > 1. offset error 4, 5 75/gain v typ chop disabled. 0.5 v typ chop enabled. offset error drift vs. temperature 5 100/gain nv/c typ gain = 1 to 16. chop disabled. 5 nv/c typ gain = 32 to 128. chop disabled. 5 nv/c typ chop enabled. offset error drift vs. time 25 nv/1000 hours typ gain 32. gain error 4 b grade 0.005 % max 0.001 % typical, gain = 1, t a = 25c, av dd = 5 v 6 . wb grade 0.0075 % max 0.001 % typical, gain = 1, t a = 25c, av dd = 5 v 6 . 0.0075 % typ gain > 1, post internal full-scale calibration. gain drift vs. temperature 1 ppm/c typ gain drift vs. time 10 ppm/1000 hours typ gain = 1. power supply rejection 95 db typ gain = 1, v in = 1 v. b grade 100 db min gain > 1, v in = 1 v/gain. 110 db typical. wb grade 95 db min gain > 1, v in = 1 v/gain. 110 db typical. common-mode rejection @ dc 100 db min gain = 1, v in = 1 v 2 . 110 db min gain > 1, v in = 1 v/gain. @ 50 hz, 60 hz 2 120 db min 10 hz output data rate, 50 1 hz, 60 1 hz. @ 50 hz, 60 hz 2 120 db min 50 1 hz (50 hz output data rate), 60 1 hz (60 hz output data rate). normal mode rejection 2 sinc 4 filter internal clock @ 50 hz, 60 hz 100 db min 10 hz output data rate, 50 1 hz, 60 1 hz. 74 db min 50 hz output data rate, rej60 7 = 1, 50 1 hz, 60 1 hz. @ 50 hz 96 db min 50 hz output data rate, 50 1 hz. @ 60 hz 97 db min 60 hz output data rate, 60 1 hz.
AD7190 data sheet rev. c | page 4 of 40 parameter AD7190b unit test conditions/comments 1 external clock @ 50 hz, 60 hz 120 db min 10 hz output data rate, 50 1 hz, 60 1 hz. 82 db min 50 hz output data rate, rej60 7 = 1, 50 1 hz, 60 1 hz. @ 50 hz 120 db min 50 hz output data rate, 50 1 hz. @ 60 hz 120 db min 60 hz output data rate, 60 1 hz. sinc 3 filter internal clock @ 50 hz, 60 hz 75 db min 10 hz output data rate, 50 1 hz, 60 1 hz. 60 db min 50 hz output data rate, rej60 = 1, 50 1 hz, 60 1 hz. @ 50 hz 70 db min 50 hz output data rate, 50 1 hz. @ 60 hz 70 db min 60 hz output data rate, 60 1 hz. external clock @ 50 hz, 60 hz 100 db min 10 hz output data rate, 50 1 hz, 60 1 hz. 67 db min 50 hz output data rate, rej60 7 = 1, 50 1 hz, 60 1 hz. @ 50 hz 95 db min 50 hz output data rate, 50 1 hz. @ 60 hz 95 db min 60 hz output data rate, 60 1 hz. analog inputs differential input voltage ranges v ref /gain v nom v ref = refinx(+) ? refinx(?), gain = 1 to 128. (av dd C 1.25 v)/gain v min/max gain > 1. absolute ain voltage limits 2 unbuffered mode agnd ? 50 mv v min av dd + 50 mv v max buffered mode agnd + 250 mv v min av dd ? 250 mv v max analog input current buffered mode input current 2 2 na max gain = 1. 3 na max gain > 1. input current drift 5 pa/c typ unbuffered mode input current 5 a/v typ gain = 1, input curren t varies with input voltage. 1 a/v typ gain > 1. input current drift 0.05 na/v/c typ external clock. 1.6 na/v/c typ internal clock. reference input refin voltage av dd v nom refin = refinx(+) ? refinx(?). reference voltage range 2 1 v min av dd v max the differential input must be limited to (av dd C 1.25 v)/gain when gain > 1. absolute refin voltage limits 2 agnd C 50 mv v min av dd + 50 mv v max average reference input current 7 a/v typ average reference input current drift 0.03 na/v/c typ external clock. 1.3 na/v/c typ internal clock.
data sheet AD7190 rev. c | page 5 of 40 parameter AD7190b unit test conditions/comments 1 normal mode rejection 2 same as for analog inputs common-mode rejection 95 db typ reference detect levels 0.3 v min 0.6 v max temperature sensor accuracy 2 c typ applies after user calibration at 25c. sensitivity 2815 codes/c typ bipolar mode. bridge power-down switch r on 10 max allowable current 2 30 ma max continuous current. burnout currents ain current 500 na nom analog inputs must be buffered and chop disabled. digital outputs (p0 to p3) output high voltage, v oh 2 4 v min av dd = 5v, i source = 200 a. output low voltage, v ol 2 0.4 v max av dd = 5v, i sink = 800 a. floating-state leakage current 100 na max floating-state output capacitance 10 pf typ internal/external clock internal clock frequency 4.92 4% mhz min/max duty cycle 50:50 % typ external clock/crystal 2 frequency 4.9152 mhz nom 2.4576/5.12 mhz min/max input low voltage, v inl 0.8 v max dv dd = 5 v. 0.4 v max dv dd = 3 v. input high voltage, v inh 2.5 v min dv dd = 3 v. 3.5 v min dv dd = 5 v. input current 10 a max logic inputs input high voltage, v inh 2 2 v min input low voltage, v inl 2 0.8 v max hysteresis 2 0.1/0.25 v min/v max input currents 10 a max logic output (dout/rdy ) output high voltage, v oh 2 dv dd ? 0.6 v min dv dd = 3 v, i source = 100 a. output low voltage, v ol 2 0.4 v max dv dd = 3 v, i sink = 100 a. output high voltage, v oh 2 4 v min dv dd = 5 v, i source = 200 a. output low voltage, v ol 2 0.4 v max dv dd = 5 v, i sink = 1.6 ma. floating-state leakage current 10 a max floating-state output capacitance 10 pf typ data output coding offset binary system calibration 2 full-scale calibration limit 1.05 fs v max zero-scale calibration limit ?1.05 fs v min input span 0.8 fs v min 2.1 fs v max
AD7190 data sheet rev. c | page 6 of 40 parameter AD7190b unit test conditions/comments 1 power requirements 8 power supply voltage av dd ? agnd 4.75/5.25 v min/max dv dd ? dgnd 2.7/5.25 v min/max power supply currents ai dd current 1 ma max 0.85 ma typical, gain = 1, buffer off. 1.3 ma max 1.1 ma typical, gain = 1, buffer on. b grade 4.5 ma max 3.5 ma typical, gain = 8, buffer off. 4.75 ma max 4 ma typical, gain = 8, buffer on. 6.2 ma max 5 ma typical, gain = 16 to 128, buffer off. 6.75 ma max 5.5 ma typical, gain = 16 to 128, buffer on. wb grade 5 ma max 3.5 ma typical, gain = 8, buffer off. 5.3 ma max 4 ma typical, gain = 8, buffer on. 6.8 ma max 5 ma typical, gain = 16 to 128, buffer off. 7.4 ma max 5.5 ma typical, gain = 16 to 128, buffer on. di dd current 0.4 ma max 0.35 ma typical, dv dd = 3 v. 0.6 ma max 0.5 ma typical, dv dd = 5 v. 1.5 ma typ external crystal used. i dd (power-down mode) b grade 2 a max wb grade 5 a max 1 temperature range: t min = ?40c, t max = +105c. 2 specification is not production tested but is supported by characterization data at initial product release. 3 fs = decimal equivalent of bit fs9 to bit fs0 in the mode register. 4 following a system or internal zero-scale calibration, the offset erro r is in the order of the no ise for the pro grammed gain a nd output data rate selected. a system full- scale calibration reduces the gain erro r to the order of the no ise for the programmed gain and output data rate. 5 the analog inputs are confi gured for differential mode. 6 applies at the factory ca libration conditions (av dd = 5 v, gain = 1, t a = 25 c ). 7 rej60 is a bit in the mode register. when the output data rate is set to 50 hz, setting rej60 to 1 places a notch at 60 hz, al lowing simultaneous 50 hz/60 hz rejection. 8 digital inputs equal to dv dd or dgnd.
data sheet AD7190 rev. c | page 7 of 40 timing characteristi cs av dd = 4.75 v to 5.25 v , dv dd = 2.7 v to 5.25 v , agnd = d gnd = 0 v, input logic 0 = 0 v, input logic 1 = dv dd , unless otherwise noted. table 2. parameter limit at t min , t max (b version) unit conditions/comments 1 , 2 t 3 100 ns min sclk high pulse width t 4 100 ns min sclk low pulse width read operation t 1 0 ns min cs falling edge to dout/ rdy active time 60 ns max dv dd = 4.75 v to 5.25 v 80 ns max dv dd = 2.7 v to 3.6 v t 2 3 0 ns min sclk active edge to data valid delay 4 60 ns max dv dd = 4.75 v to 5.25 v 80 ns max dv dd = 2.7 v to 3.6 v t 5 5 , 6 10 ns min bus relinquish time after cs inactive edge 80 ns max t 6 0 ns min sclk inactive edge to cs inactive edge t 7 10 ns min sclk inactive edge to dout/ rdy high write operation t 8 0 ns min cs falling edge to sclk active edge setup time 4 t 9 30 ns m in data valid to sclk edge setup time t 10 25 ns min data valid to sclk edge hold time t 11 0 ns min cs rising edge to sclk edge hold time 1 s ample tested during initial release to ensure compliance. all input signals are specified with t r = t f = 5 ns (10% to 90% of dv dd ) and timed from a voltage level of 1.6 v. 2 see figure 3 and figure 4 . 3 these numbers are measured with the load cir cuit shown in figure 2 and defined as the time required for the output to cross the v ol or v oh limits. 4 the sclk active edge is the falling edge of sclk. 5 these numbers are derived from the measured time taken by the data output to change 0.5 v when loaded with the circuit sh own in figure 2 . the measured number is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the times quoted in the timing characteristics are the true bus relinquish tim es of the part and, as such, are independent of external bus loading capacitances. 6 rdy retu rns high after a read of the data register. in single conversion mode and continuous conversion mode, the same data can be read again, if required, while rdy is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. if the continuous read feature is enabled , the digital word can be read only once. circuit and timing d iagrams i sink (1.6ma with dv dd = 5v, 100a with dv dd = 3v) i source (200a with dv dd = 5v, 100a with dv dd = 3v) 1.6v to output pin 50pf 07640-002 figure 2 . load circuit for timing characterization
AD7190 data sheet rev. c | page 8 of 40 t 2 t 3 t 4 t 1 t 6 t 5 t 7 cs (i) dout/rdy (o) sclk (i) i = input, o = output msb lsb 07640-003 figure 3 . read cycle timing diagram i = input, o = output cs (i) sclk (i) din (i) msb lsb t 8 t 9 t 10 t 11 07640-004 figure 4 . write cycle timing diagram
data sheet AD7190 rev. c | page 9 of 40 absolute maximum rat ings t a = 25c, unless otherwise noted. table 3. parameter rating av dd to a gnd ? 0.3 v to + 6.5 v dv dd to a gnd ? 0.3 v to + 6.5 v agnd to dgnd ? 0.3 v to + 0.3 v analog input voltage to a gnd ? 0.3 v to av dd + 0.3 v reference input voltage to a gnd ? 0.3 v to av dd + 0.3 v digital input voltage to d gnd ? 0.3 v to dv dd + 0.3 v digital output voltage to d gnd ? 0.3 v to dv dd + 0.3 v ain/digital input current 10 ma operating temperature range ? 40c to +105c storage temperature range ? 65c to +150c maximum junction temperature 150c lead te mperature, soldering reflow 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 4 . thermal resistance package type ja jc unit 24- lead tssop 128 42 c/w esd caution
AD7190 data sheet rev. c | page 10 of 40 pin configuration and function descriptions nc = no connect 1 2 3 4 5 6 7 8 9 10 12 11 mclk2 sclk cs p1/refin2(+) p2 p3 mclk1 p0/refin2(?) nc aincom ain2 ain1 20 21 22 23 24 19 18 17 16 15 14 13 dout/rdy sync dv dd agnd dgnd av dd bpdsw refin1(?) ain3 ain4 refin1(+) din AD7190 top view (not to scale) 07640-005 figure 5 . pin configuration table 5 . pin function descriptions pin no. mnemonic description 1 mclk1 when the master clock for the device is provided externally by a crys tal, the crystal i s connected between mclk1 and mclk2. 2 mclk2 master clock signal for the d evice. the AD7190 h as an internal 4.92 mhz clock. this internal clock can be made available on the mclk2 pin. the clock for the AD7190 can be provided extern ally also in the form of a crystal or external clock. a crystal can be tied across the mclk1 and mclk2 pins. alternatively, the mclk2 pin can be driven with a cmos - compatible clock and the mclk1 pin left unconnected. 3 sclk serial clock input. this seri al clock input is for data transfers to and from the adc. the sclk has a schmitt - triggered input, making the interface suitable for opto - isolated applications. the serial clock can be continuous with all data transmitted in a continuous train of pulses. al ternatively, it can be a noncon - tinuous c lock with the information transmitted to or from the adc in smaller batches of data. 4 cs chip select input. this is an active low logic input used to select the adc. cs can be used to select the adc in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. cs can be hardwired low, allowing the adc to operate in 3 - wire mode with s clk, din, and dout used to interface with the device. 5 p3 digital output pin. this pin can function as a general - purpose output bit referenced between av dd and agnd. 6 p2 digital output pin. t his pin can function as a general - purpose output bit referen ced between av dd and agnd. 7 p 1/refin2(+) digital output pin /positive reference input . this pin function s as a general - purpose output bit referenced between av dd and a gnd. when refsel = 1, this pin functions as refin2(+). a n external reference can be appl ied between refin2(+) and refin 2 (?). refin2(+) can lie anywhere between av dd and a gnd + 1 v. the nominal reference voltage, ( refin2(+) ? refin 2 (?)), is av dd , but the part fu nctions with a reference from 1 v to av dd . 8 p 0/refin2( ?) digital output pin /nega tive reference input . this pin function s as a general - purpose output bit referenced between av dd and a gnd. when refsel = 1, this pin functions as refin2( ? ). this reference input can lie anywhere between a gnd and av dd ? 1 v. 9 nc no connect. this pin shoul d be tied to agnd. 10 aincom a nalog i nput ain1 to analog input ain4 are referenced to this i nput when configured for pseudo differential operation . 11 ain1 analog input. it can be configured as the positive input of a fully differential input pair when used with ain2 or as a ps eudo differential input when used with aincom . 12 ain 2 analog input. it can be configured as the negative input of a fully differential input pair when used with ain1 or as a pseudo differential input when used with aincom .
data sheet AD7190 rev. c | page 11 of 40 pin no. mnemonic description 13 a in3 analog input. it can be configured as the positive input of a fully differential input pair when used with ain4 or as a pseudo differential input when used with aincom. 14 ain 4 analog input. it can be configured as the nega tive input of a fully differ ential input pair when used with ain 3 or as a pseudo differential input when used with aincom . 15 refin1(+) positive reference input. an external reference can be applied between refin1(+) and refin 1 (?). refin1(+) can lie anywhere between av dd and a gnd + 1 v. the nominal reference voltage, ( refin1(+) ? refin 1 (?)), is av dd , but the part fu nctions with a reference from 1 v to av dd . 16 refin 1 (?) negative reference input. this reference input can lie a nywhere between a gnd and av dd ? 1 v. 17 bpdsw bridge p ower - down s witch to agnd. 18 agnd analog ground reference point. 19 dgnd digital ground reference point. 20 av dd analog su pply voltage, 4.75 v to 5.25 v. a v dd is independent of dv dd . 21 dv dd digit al supply voltage, 2.7 v to 5.25 v. dv dd is independent of av dd . 22 sync logic i nput that allows for synchronization of the digital filters and analog modulators when using multiple AD7190 devices. while sync is low, the nodes of the digital filter, the filter control logic , and the calibration control logic are reset and the analog modulator is held in its reset state. sync does not affect the digital interface but does reset rdy to a high state if it is low. sync has a pull - up resistor internally to dv dd . 23 dout/ rdy serial data output/data ready output. dout/ rdy serves a dual purpose. it functio ns as a serial data output pin to access the output shift register of the adc. the output shift register can contain data from any of the on - chip data or control registers. in addition, dout/ rdy operates as a data ready pin, going lo w to indicate the completion of a conversion. if the data is not read after the conversion, the pin go es high before the next update occurs. the dout/ rdy falling edge can be used as an interrupt to a processor, indicating that valid data is available. with an external serial clock, the data can be read using the dout/ rdy pin. with cs low, the data/control word information is placed on the dout/ rdy pin on the sclk fa lling edge and is valid on the sclk rising edge. 24 din serial data input to the input shift register on the adc. data in this shift register is transferr ed to the control registers in the adc, with the register selection bits of the communications register identifying the appropriate register.
AD7190 data sheet rev. c | page 12 of 40 typical performance characteristics 8,388,760 8,388,758 8,388,756 8,388,754 8,388,752 8,388,750 8,388,748 8,388,746 0 200 400 600 800 1000 code sample 07640-106 figure 6. noise (v ref = 5 v, output data rat e = 4.7 hz , gain = 128 , chop disabled, sinc 4 filter ) 250 200 150 100 50 0 8,388,746 8,388,748 8,388,750 8,388,752 8,388,754 8,388,756 8,388,758 8,388,760 frequency code 07640-107 figure 7. noise di stribution histogram (v ref = 5 v, output data rate = 4.7 h z, gain = 128 , chop disabled, sinc 4 filter ) 8,388,950 8,388,900 8,388,800 8,388,750 8,388,650 8,388,600 8,388,850 8,388,700 8,388,550 8,388,500 8,388,450 0 200 400 600 800 1000 100 300 500 700 900 code samples 07640-108 figure 8. noise ( v ref = 5 v, output data rat e = 4800 hz , gain = 1 28 , chop disabled, sinc 4 filter ) 30 20 25 15 10 5 0 8,388,490 8,388,576 8,388,662 8,388,748 8,388,834 8,388,920 frequency code 07640-109 figure 9. noise distribution histogram (v ref = 5 v, output data rate = 4800 h z, gain = 128 , chop disabled, sinc 4 filter )
data sheet AD7190 rev. c | page 13 of 40 8,388,820 8,388,800 8,388,760 8,388,740 8,388,700 8,388,680 8,388,780 8,388,720 8,388,660 8,388,640 8,388,620 0 200 400 600 800 1000 100 300 500 700 900 code samples 07640-110 figure 10 . noise ( v ref = 5 v, output data rat e = 4800 hz , gain = 1 , chop disabled, sinc 4 filter ) 80 50 70 40 60 30 20 10 0 8,388,620 8,388,660 8,388,700 8,388,740 8,388,780 8,388,820 frequency code 07640-111 f igure 11 . noise distribution histogram (v ref = 5 v, output data rate = 4800 hz, gain = 1, chop disabled, sinc 4 filter) 3.0 2.0 1.0 0 ?1.0 ?2.0 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 inl (ppm of fsr) v in (v) 07640-112 figure 12 . inl (gain = 1) 6 4 2 0 ?2 ?4 ?6 ?0.020 ?0.015 ?0.010 ?0.005 0 0.005 0.010 0.015 0.020 inl (ppm of fsr) v in (v) 07640-113 figure 13 . inl (gain = 128)
AD7190 data sheet rev. c | page 14 of 40 66 64 62 60 58 56 54 ?60 ?40 ?20 0 20 40 60 80 100 120 140 output voltage (v) temperature (c) 07640-114 figure 14 . offset error (gain = 1, chop disabled) 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 ?0.6 ?0.7 ?60 ?40 ?20 0 20 40 60 80 100 120 offset (v) temerature (c) 07640-115 figure 15 . offset error (gain = 128, chop disabled ) 1.000008 1.000007 1.000006 1.000005 1.000004 1.000003 1.000002 1.000001 1.000000 ?60 ?40 ?20 0 20 40 60 80 100 120 gain temperature (c) 07640-116 figure 16 . gain error (gain = 1 , chop disabled ) 128.003 128.002 128.001 128.000 127.999 127.998 127.997 127.996 ?60 ?40 ?20 0 20 40 60 80 100 120 gain temperature (c) 07640-117 figure 17 . gain error ( gain = 128 , chop disabled )
data sheet AD7190 rev. c | page 15 of 40 rms noise and resolu tion the AD7190 has a choice of two filter types: sinc 4 and sinc 3 . in addition, the AD7190 can be operated with chop enabled or chop disabled. the following tables sho w the rms noise of the AD7190 for some of the output data rate s and gain settings with chop disabled and enabled for the sinc 4 and sinc 3 filters . the numbers given are for the bi polar input range with the external 5 v reference. these numbers are typical a nd are generated with a differential input voltage of 0 v when the adc is continuously converting on a single channel . t he effective resolution is also shown, and the output peak - to - peak (p - p) resolution , or noise - free resol - ution , is listed in parentheses . it is important to note that the effective resolution is calc u lated using the rms noise, wh eras the p- p resolution is calculate d based on peak - to - peak noise. the p- p resolution repr e sents the resolution for which there is no code flicker. these numbers a re typical and are rounded to the nearest ? lsb. sinc 4 c hop d isabled table 6 . rms noise ( n v) vs. gain and output data r ate filter word (decimal) output data rate (hz) settling time (ms) gain of 1 gain of 8 gain of 16 gain of 32 g ain of 64 gain of 128 1023 4.7 852.5 250 38 21 12 10 8.5 640 7.5 533 310 45 25 16 12 10.5 480 10 400 330 50 30 18 14 11.5 96 50 80 900 125 78 45 33 28 80 60 66.7 970 140 88 52 36 31 32 150 26.7 1460 215 125 75 55 48 16 300 13.3 1900 285 170 100 75 67 5 960 4.17 3000 480 280 175 140 121 2 2400 1.67 5000 780 440 280 220 198 1 4800 0.83 14, 300 1920 1000 550 380 295 table 7 . effective resolution ( peak -to -p eak resolution ) vs. gain and output data r ate filter word (decimal) o utput data rate (hz) settling time (ms) gain of 1 1 gain of 8 1 gain of 16 1 gain of 32 1 gain of 64 1 gain of 128 1 1023 4.7 852.5 24 (22.5) 24 (22) 24 (22) 24 (22) 24 (21) 23 (20.5) 640 7.5 533 24 (22) 24 (22) 24 (22) 24 (21.5) 23.5 (21) 23 (20) 480 10 40 0 24 (22) 24 (22) 24 (21.5) 24 (21.5) 23 .5 (20.5) 22.5 (20) 96 50 80 23.5 (20.5) 23.5 (20.5) 23 (20) 22.5 (20) 22 (19.5) 21.5 (18.5) 80 60 66.7 23.5 (20.5) 23 (20.5) 22.5 (20) 22.5 (20) 22 (19.5) 21.5 (18.5) 32 150 26.7 22.5 (20) 22.5 (19.5) 22.5 (19.5 ) 22 (19.5) 21.5 (18.5) 20.5 (18) 16 300 13.3 22.5 (19.5) 22 (19.5) 22 (19) 21.5 (19) 21 (18.5) 20 (17.5) 5 960 4.17 21.5 (19) 21.5 (18.5) 21 (18.5) 21 (18) 20 (17.5) 19.5 (16.5) 2 2400 1.67 21 (18) 20.5 (18) 20.5 (17.5) 20 (17.5) 19.5 (16.5) 18.5 (16 ) 1 4800 0.83 19.5 (16.5) 19.5 (16.5) 19.5 (16.5) 19 (16.5) 18.5 (16) 18 (15.5) 1 t he output pe ak - to - peak (p - p) resolution is listed in parentheses.
AD7190 data sheet rev. c | page 16 of 40 s inc 3 c hop d isabled table 8 . rms noise ( nv) vs. gain and output data rate filter word (decimal) output data rate (hz) settling time (ms) gain of 1 gain of 8 gain of 16 gain of 32 gain of 64 gain of 128 1023 4.7 639.4 270 42 23 13.5 10.5 9 640 7.5 400 320 50 27 17 13 11.5 480 10 300 350 60 35 19 15 12.5 96 50 60 1000 134 86 50 35 29 80 60 50 1050 145 95 55 40 32 32 150 20 1500 225 130 80 58 50 16 300 10 1950 308 175 110 83 73 5 960 3.125 4000 590 330 200 150 133 2 2400 1.25 56, 600 7000 3500 1800 900 490 1 4800 0.625 442, 000 55,0 00 28, 000 14, 000 7000 3450 table 9 . effective resol ution ( peak -to - peak resolution ) vs. gain and output data rate filter word (decimal) output data rate (hz) settling time (ms) gain of 1 1 gain of 8 1 gain of 16 1 gain of 32 1 gain of 64 1 gain of 128 1 1023 4.7 639.4 24 (22.5) 24 (22) 24 (22) 24 (21.5) 24 (21) 23 (20.5) 640 7.5 400 24 (22) 24 ( 22) 24 (21.5) 24 (21.5) 23.5 (21) 22.5 (20) 480 10 300 24 (22) 24 (21.5) 24 (21.5) 24 (21) 23.5 (20.5) 22.5 (20) 96 50 60 23 .5 (20.5) 23 (20.5) 23 (20) 22.5 (20) 22 (19.5) 21 .5 (18.5) 80 60 50 23 (20.5) 23 (20.5) 22.5 (20) 22.5 (19.5) 22 (19) 21 (18.5 ) 32 150 20 22.5 (20) 22.5 (19.5) 22 (19.5) 22 (19) 21.5 (18.5) 20.5 (18) 16 300 10 22.5 (19.5) 22 (19) 22 (19) 21.5 (18.5) 21 (18) 20 (17.5) 5 960 3.125 21.5 (18.5) 21 (18.5) 21 (18) 20.5 (18) 20 (17.5) 19 (16.5) 2 2400 1.25 17 .5 (14.5) 17 .5 (14.5) 17 .5 (14.5) 17 .5 (14.5) 17 .5 (14.5) 17 .5 (14.5) 1 4800 0.625 14.5 (11.5) 14.5 (1 1.5 ) 14.5 (11.5) 14.5 (11.5) 14.5 (11.5) 14.5 (11.5) 1 t he output peak - to - peak (p - p) resolution is listed in parentheses.
data sheet AD7190 rev. c | page 17 of 40 sinc 4 chop e nabled table 10 . rms noise ( n v) vs. gain and output data rate filter word (decimal ) output data rate (hz) settling time (ms) gain of 1 gain of 8 gain of 16 gain of 32 gain of 64 gain of 128 1023 1.175 1702 177 27 15 8.5 7 6 640 1.875 1067 219 32 18 11.5 8.5 7.5 480 2.5 800 234 36 21 13 10 8.5 96 12.5 160 637 89 55 32 24 20 80 15 1 33 686 99 63 37 26 22 32 37.5 53 1033 152 89 53 39 34 16 75 26.7 1343 202 120 71 53 48 5 240 8.33 2121 340 198 124 99 86 2 600 3.33 3536 552 311 198 156 140 1 1200 1.67 10, 200 1360 707 389 26 209 table 11 . effective resolutio n ( peak -to - peak resolution ) vs. gain and output data ra te filter word (decimal) output data rate (hz) settling time (ms) gain of 1 1 gain of 8 1 gain of 16 1 gain of 32 1 gain of 64 1 gain of 128 1 1023 1.175 1702 24 (23) 24 (22.5) 24 (22.5) 24 (22.5) 24 (21.5) 23.5 (21) 640 1.875 1067 24 (22.5) 24 (22.5) 24 (22.5) 24 (22) 24 (21.5) 23.5 (20.5) 480 2.5 800 24 (22.5) 24 (22.5) 24 (22) 24 (22) 24 (21) 23 (20.5) 96 12.5 160 24 (21) 24 (21) 23.5 (20.5) 23 (20.5) 22.5 (20) 22 (19) 80 15 133 24 (21) 23.5 (21) 23.5 (20.5) 23 (20.5) 22.5 (20) 22 (19) 32 37.5 53 23 (20.5) 23 (20) 23 (20) 22.5 (20) 22 (19) 21 (18.5) 16 75 26.7 23 (20) 22.5 (20) 22.5 (19.5) 22 (19.5) 21.5 (19) 20.5 (18) 5 240 8.33 22 (19.5) 22 (19) 21.5 (19) 21.5 (18.5) 20.5 (18) 20 (17) 2 600 3.33 21.5 (18.5) 21 (18.5) 21 (18) 20.5 (18) 20 (17) 19 (16.5) 1 1200 1.67 20 (17) 20 (17) 20 (17) 19.5 (17) 19 (16.5) 18.5 (16) 1 t he output peak - to - peak (p - p) resolution is listed in parentheses.
AD7190 data sheet rev. c | page 18 of 40 s inc 3 chop e nabled table 12 . rms noise ( nv) vs. gain and output data rate filter word (decimal) outp ut d ata r ate (hz) settling time (ms) gain of 1 gain of 8 gain of 16 gain of 32 gain of 64 gain of 128 1023 1.56 1282 191 30 16.5 10 8 6.5 640 2.5 800 226 36 19 12 9 8.5 480 3.33 600 248 43 25 14 11 9 96 16.6 120 708 95 61 36 25 21 80 20 100 743 103 68 39 29 23 32 50 40 1061 159 92 57 41 36 16 100 20 1380 218 124 78 59 52 5 320 6.25 2829 418 234 142 106 94 2 800 2.5 40, 100 4950 2475 1273 637 347 1 1600 1.25 312, 550 38, 540 19, 800 9900 4950 2440 table 13. effective resolu tio n ( peak -to - peak resolution ) vs. gain and output data rate filter word (decimal) output data rate (hz) settling time (ms) gain of 1 1 gain of 8 1 gain of 16 1 gain of 32 1 gain of 64 1 gain of 128 1 1023 1.56 1282 24 (23) 24 (22.5) 24 (22.5) 24 (22) 24 (21.5) 23.5 (21) 640 2.5 800 24 (22.5) 24 (22.5) 24 (22) 24 (22) 24 (21.5 ) 23 (20.5) 480 3.33 600 24 (22.5) 24 (22) 24 (22) 24 (21.5) 24 (21) 23 (20.5) 96 16.6 120 24 (21) 23.5 (21) 23 .5 (20.5) 23 (20.5) 22.5 (20) 22 (19) 80 20 100 23.5 (21) 23.5 (21) 23 (20.5) 23 (20) 22.5 (19.5) 21.5 (19) 32 50 40 23 (20.5) 23 (20) 22.5 (20) 22.5 (19.5) 22 (19) 21 (18.5) 16 100 20 23 (20) 22.5 (19.5) 22.5 (19.5) 22 (19) 21.5 (18.5) 20.5 (18) 5 320 6.25 22 (19) 21.5 (19) 21.5 (18.5) 21 (18.5) 20.5 (18) 19.5 (17) 2 800 2.5 18 (15) 18 (15) 18 (15) 18 (15) 18 (15) 18 (15) 1 1600 1.25 15 (12) 15 (12.5) 1 5 (12) 1 5 (12) 1 5 (12) 1 5 (12) 1 t he output peak - to - peak (p - p) resolution is listed in paren theses.
data sheet AD7190 rev. c | page 19 of 40 on- chip registers the adc is controlled and configured via a number of on - chip registers, which are described i n the following sections. in the descriptions, set implies a logic 1 state and cleared implies a logic 0 state, unless otherwise noted. communications regis ter (rs2, rs1, rs0 = 0, 0, 0) the communications register is an 8 - bit write - only register. all communications to the part must start with a write operation to the communications register. the data written to the communi - cations register determines whether the next operation is a read or write operation and in which register this operation takes place. for read or write operations, when the subsequent read or write operation to the selected regi ster is complete, the interface returns to where it expects a write operation to the communi cations register. this is the default state of the interface and, on power - up or after a reset, the adc is in this default state waiting for a write operation to the communi - cations register. in situations where the interface sequence is lost, a write operation of at least 40 serial clock cycles with din high returns the adc to this default state by resetting the entire part. table 14 o utlines the bit designations for the communications register. cr0 through cr7 indicate the bit location s , cr denoting that the bits are in the communications register. cr7 denotes the first bit of the data stream. the number in parentheses indicates the po wer - on/reset default status of that bit. cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 wen (0) r/ w (0) rs2(0) rs1(0) rs0(0) cread(0) 0(0) 0(0) table 14 . communications register bit designations bit location bit name description cr7 wen write e nable b it. a 0 must be written to this bit for a write to the communications register to occur. if a 1 is the first bit written, the part does not clock on to subsequ en t bits in the register. it stay s at this bit location until a 0 is written to this bit. after a 0 is written to the wen bit, the next seven bits are loaded to the communications register. cr6 r/ w a 0 in th is bit location indicates that the next operation is a write to a specified register. a 1 in this position indicates that the next operation is a read from the designated register. cr5 to cr3 rs2 to rs0 register address b its. these address bits are use d to select which registers of the adc are selected during the serial interface communication. see table 15. cr2 cread continuous read of the data r egister. when this bit is set to 1 (and the data register is selected), the serial interface is configured so that the data re gister can be continuously read; that is, the contents of the data register are automatically placed on the dout pin when the sclk pulses are applied after the rdy pin goes low to in dicate that a conversion is complete. the communications register does not have to be written to for subsequent data reads. to enable continuous read , the instruction 01011100 must be written to the commu nications register. to disable continuous read , the instruction 01011000 must be written to the communications register while the rdy pin is low. while continuous read is enabled, the adc monitors activity on the din line so that it can receive the instruction to disable continuous re ad . additi onally, a reset occur s if 40 consecutive 1s are seen on din. therefore, din should be held low until an instruction is to be written to the device. cr1 to cr0 these bits must be programmed to logic 0 for correct operation. table 15 . register selection rs2 rs1 rs0 register register size 0 0 0 communications r egiste r during a write o peration 8 bit s 0 0 0 status register during a read o peration 8 bit s 0 0 1 mode r egister 24 bit s 0 1 0 configurat ion r egister 24 bit s 0 1 1 data register/d ata r egister plus status i nformation 24 bit s/ 32 bit s 1 0 0 i d r egister 8 bit s 1 0 1 gpocon r egister 8 bit s 1 1 0 offset r egister 24 bit s 1 1 1 full - scale r egister 24 bit s
AD7190 data sheet rev. c | page 20 of 40 status regis ter (rs2, rs1, rs0 = 0, 0, 0; power - on/reset = 0x8 0) the status register is an 8 - bit , read - only register. to access the adc status register, the user must write to the communications register, select the next operation to be a read, and load bit rs2, bit r s1, and bit rs0 with 0. table 16 outlines the bit designations for the status register. sr0 through sr7 indicate the bit locations, sr denoting that the bits are in the status register. sr7 denotes the first bit of the data str eam. the number in parentheses indicates the power - on/reset default status of that bit. sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 rdy (1) err(0) noref(0) parity( 0) 0 (0) chd2(0) ch d 1(0) ch d 0(0) table 16. status register bit designations bit location bit name description sr7 rdy ready b it for the adc. cleare d when data is written to the adc data register. the rdy bit is set automatically after the adc data register is read , or a period of time before the data register is updated with a new conversion result , to indicate to the user that the conversion data should not be read. it is also set when the part is placed in power - down mode or idle mode or when sync is taken low . the end of a conversion is also indicated by the dout/ rdy pin. this pin can be used as an alternative to the status register for monitoring the adc for conversion data. sr6 err adc e rror b it . this bit is written to at the same time as the rdy bit. the err bit is s et to indicate that the result written to the adc data register is clamped to all 0s or all 1s. error sources include overrange or underrange or the absence of a reference voltage. the bit is c leared by a write operation to start a conversion. sr5 noref no external reference b it. this bit is s et to indicate that the selected reference (refin1 or refin2) is at a voltage that is below a specified threshold. wh en set, conversion results are clamped to all 1s . this bit is c leared to indicate that a valid reference is applied to the selected reference pins. the noref bit is e nabled by setting the ref det bit in the configuration register to 1. sr4 p arity parity check of the data r egister. if the enpar bit in the mode register is set, the parity bit is set if there is an odd number of 1s in the data register. it is cleared if there is an even number of 1s in the data register. the dat_sta bit in the mode register should be set when the parity check is used. when the dat_sta bit is set, the contents of the status register are transmitted along with the data for each data register read. sr3 0 this bit will be set to 0. sr2 to sr0 ch d2 to ch d 0 these bits indicate which channel corresponds to the data register contents. they do not indicate which channel is presently being converted but indicate which channel was selected when the conversion containe d in the data register was generated. mode register (rs2, rs1, rs 0 = 0, 0, 1; power - on/reset = 0x0 80 060) the mode register is a 24 - bit register from which data can be read or to which data can be written. this register is used to select the operating mode, the output data rate , and the clock source. table 17 outlines the bit designations for th e mode register. mr0 through mr23 indicate the bit locations, mr denoting that the bit s are in the mode register. mr23 denotes the first bit of the data stream. the number in parentheses indicates the power - on/reset default status of that bit. any write to the mode register resets the modulator and filter and sets the rdy bit. mr23 mr22 mr21 mr20 mr19 mr18 mr17 mr16 md2(0) md1(0) md0(0) dat_sta (0) clk1( 1) clk 0 (0) 0 0 mr15 mr14 mr13 mr12 mr11 mr10 mr9 mr8 sinc3 (0) 0 enpar(0) 0 single (0) rej60(0) fs9 (0) fs8 (0) mr7 mr6 mr5 mr4 mr3 mr2 mr1 mr0 fs7(0 ) fs6(1) fs5(1) fs4 (0) fs3 (0) fs2 (0) fs1( 0 ) fs0(0)
data sheet AD7190 rev. c | page 21 of 40 table 17 . mode register bit designations bit location bit name description mr23 to mr21 md2 to md0 mode s elect b its. these bits select the operati ng mode of the AD7190 (see table 18). mr20 dat_sta this bit enables the t ransmi s s ion of status register contents a fter each data register read. when dat_sta is set, the contents of the status register are transmitted along with each data register read. this function is useful when several channels are selected because the status register identifies the channel to whic h the data register value corresponds. mr 19 to mr 18 clk1 to clk0 these bits are used to select the clock source for the AD7190. either the on - chip 4.92 m hz clock or an external clock can be used. the ability to use an external clock allows several ad719 0 devices to be synchronized. also, 50 hz/60 hz rejection is improved when an accurate external clock drives the AD7190 . clk1 clk0 adc clock source 0 0 external c rystal . the external crystal is connected from mclk1 to mclk2. 0 1 external clock . the external clock is applied to the mclk2 pin. 1 0 internal 4.92 m hz clock. pin mclk2 is tri stated. 1 1 internal 4.92 m hz clock. the internal clock is available on mclk2. mr 17 to mr16 these bit s must be programmed with a logic 0 for c orrect operation. mr 15 sinc3 sinc 3 f ilter s elect b it . when this bit is cleared, the sinc 4 filter is used (default value). when this bit is set, the s inc 3 filter is used. the benefit of the sinc 3 filter compared to the sinc 4 filter is its lower settling t ime when chop is disabled. for a given output data rate , f adc , the sinc 3 filter has a settling time of 3/ f adc while the sinc 4 filter has a settling time of 4/ f adc . the sinc 4 filter, due to its deeper notches, gives better 50 hz/60 hz rejection. at low outp ut data rates, both filters give similar rms noise and similar no missing codes for a given output data rate. at higher output data rates (fs values less than 5), the sinc 4 filter gives better performance than the sinc 3 filter for rms noise and no missing codes. mr14 this bit must be programmed with a logic 0 for correct operation. mr13 enpar enable parity b it. when enpar is set, parity checking on the data register is enabled. the dat_sta bit in the mode register should be set when the parity check is used. when the dat_sta bit is set, the contents of the status register are transmitted along with the data for each data register read. mr12 this bit must be programmed with a logic 0 for correct operation. mr11 s ingle single cycle conversion enable b it. when this bit is set, the AD7190 settles in one conversion cycle so that it functions as a zero latency adc. this bit has no affect when multiple analog input channels are enabled or when the single conversion mode is selected. mr10 rej60 this bit enable s a notch at 60 hz when the first notch of the sinc filter is at 50 hz. when rej60 is set, a filter notch is placed at 60 hz when the sinc filter first notch is at 50 hz. this allows simultaneous 50 hz/60 hz rejection. mr 9 to mr0 fs 9 to fs0 filter outpu t d ata r ate select b its. the 10 bits of data programmed into thes e bits determine the filter cut off frequency, the position of the first notch of the filter , and the output data rate for the part. in association with the gain selection , it also determines the output no ise (and, therefore, the effective resolution) of the device. (see table 6 through table 13 ) when chop is disabled and continuous conversion mode is selected, the output data rate equals ou tput data rate = ( fmod /64)/ fs where fs is the decimal equivalent of the code in bits fs0 to fs9 and is in the range 1 to 1023 , and fmod is the modulator frequency , which is equal to mclk/16. with a nominal mclk of 4.9 2 mh z, this results in a output data ra te from 4.69 hz to 4.8 khz. with chop disabled, the filter first notch frequency is equal to the output data rate when converting on a single channel . when chop is enabled, the output data rate equals output data rate = ( fmod /64)/ ( n fs ) w here : fs is the dec imal equivalent of the code in b it fs0 to bit fs9 and is in the range 1 to 1023 . fmod is the modulator frequency , which is equal to mclk / 16. with a nominal mclk of 4.9 2 mhz, this results in a conversion rate from 4.69 /n hz to 4.8 /n khz , where n is the order of the sinc filter . the sinc filters first notch frequency is equal to n output data rate. the chopping introduces notches at odd integer multiples of (output data rate/2).
AD7190 data sheet rev. c | page 22 of 40 table 18 . operating modes md2 md1 md0 mode 0 0 0 continuous c onversion m ode ( d efault). in continuous conversion mode, the adc continuously performs conversions and places the result in the data register . the dout/ rdy pin and the rdy bit in the statu s register go low when a conversion is complete. the user can read these conversions by setting the cread bit in the communications register to 1, which enables continuous read. when continuous read is enabled, the conversions are automatically placed on t he dout line when sclk pulses are applied. alternatively, the user ca n instruct the adc to output each conversion by writing to the communications register. after power - on, a reset, or a reconfiguration of the adc, the complete settling time of the filter is required to generate the first valid conversion. subsequent conversions are available at the selected output data rate, which is dependent on filter choice. 0 0 1 single conversion m ode. when single conversion mode is selected, the adc powers up and performs a single conversion on the selected channel . the internal clock requires up to 1 ms to power up and settle. the adc then performs the conversion , which requires the complete settling time of the filter. the conversion result is placed in the data register, rdy goes low, and the adc returns to power - down mode. the conversion remains in the data register and rdy remains active (low) until the data is read or another conversion is performed. 0 1 0 idl e m ode. in idle mode, the adc filter and modulator are held in a reset state even though the modulator clocks are still provided. 0 1 1 power - down m ode. in power - down mode, all AD7190 circuitry , except the bridge power - down switch, is powered down. the bridge power - down switch remains active because the user may need to power up the sensor prior to powering up the AD7190 for settling reasons. the external crystal, if selected, remains active. 1 0 0 internal zero - scale c alibration. an internal short is autom atically connected to the input . rdy goes high when the calibration is initiated and returns low when the calibration is complete. the adc is placed in idle mode following a calibration. the measured offset coefficient is placed in the offset register of the selected channel. 1 0 1 internal full - scale c alibration. a full - scale input voltage is automati cally connected to the input for this calibration. rdy goes high when the calibration is initiated and returns low when the calibration is complete. the adc is placed in idle mode following a calibration. the measured full - scale coefficient is placed in the full - scale register of the selected channel. a full - scale calibration is required each time the gain of a channel is changed to minimize the full - scale error. 1 1 0 system zero - s cale c alibration. the u ser should connect the system zero - scale input to the channel input pins as selected by the ch 7 to ch0 bits in the configuration register . rdy goes high when the calibration is initiated and returns low when the calibration is complete. the adc is placed in idle mode following a calibration. the measured offset coefficient is placed in the offset register of the selected channel . a system zero - scale calibration is required each time the gain of a channel is changed. 1 1 1 system full - scale c alibration. the u ser should connect the system full - scale input to the channel input pins as selected by the ch 7 to ch0 bits in the confi guration register . rdy goes high when the calibration is initiated and returns low when the calibration is complete. the adc is placed in idle mode following a calibration. the measured full - scale coefficient is placed in the full - sc ale register of the selected channel. a full - scale calibration is required each time the gain of a channel is changed. configuration regist er (rs2, rs1, rs0 = 0, 1, 0; power - on/reset = 0x 000 117) the configuration register is a 24- bit register from which data can be read or to which data can be written. this register is used to configure the adc for unipolar or bipolar mode, to enable or disable the buffer, to enable or disable the burnout currents, to select the gain, and to select the analog input channe l. table 19 outlines the bit designations for the configuration register. con0 through con 23 indicate the bit locations. con denotes that the bits are in the configuration register. con 23 denotes the first bit of the data str eam. the number in parenthese s indicates the power - on/reset default status of that bit.
data sheet AD7190 rev. c | page 23 of 40 con23 con22 con21 con20 con19 con18 con17 con16 c hop (0) 0(0) 0(0) refsel (0) 0(0) 0 (0) 0 (0) (0) con15 con14 con13 con12 con11 con10 con9 con8 ch7 (0) ch6 (0) ch5 (0) ch4 (0) ch3 (0) ch2 (0) ch1 (0) ch0 (1) con7 con6 con5 con4 con3 con2 con1 con0 b urn(0) refdet (0) 0 (0) buf(1) u/ b (0) g 2( 1 ) g 1( 1 ) g 0( 1 ) table 19 . configuration register bit designations bit locatio n bit name description con23 c hop chop e nable b it. when the chop bit is cleared, chop is disable d. when the chop bit is set, chop is en abled. when chop is enabled, the offset and offset drift of the adc are continuously minimized . however, this increas es the conversion time and settling time of the adc. for example, when fs = 96 decimal and the sinc 4 filter is selected, the conversion time with chop enabled equals 80 ms and the settling time equals 160 ms. with chop disabled, higher conversion rates are allowed. for an fs word of 96 decimal and the sinc 4 filter selected, the conversion time is 20 ms and the settling time is 80 ms. however, at low gains, periodic calibrations may be required to remove the offset and offset drift. con22, con21 these bit s must be programmed with a logic 0 for correct operation. con 20 refsel reference s elect b its. the reference source for the adc is selected using these bits. refsel reference voltage 0 external reference applied between refin1(+) and refin1 ( ? ). 1 external reference applied between the p1/refin2(+) and p0/refin2( - ) pins. con19 to con16 these bit s must be programmed with a l ogic 0 for correct operation. con15 to con8 ch7 to ch0 channel s elect b its. these bits are used to select which cha nnels are enabled on the AD7190 . see table 20. several channels can be selected , and the ad719 0 automatically sequence s them. the conversion on each channel require s the complete settling time. con7 b urn when this bi t is set to 1 , the 5 00 na current sources in the signal path are enabled. when b urn = 0, the burnout currents are disabled. the burnout currents can be enabled only when the buffer is active and when chop is disabled . con6 ref det enables the r eference d etect f unctio n. when set , the noref bit in the status register indicates when the external reference being used by the adc is open circuit or less than 0. 6 v maximum . the reference detect circuitry only operates when the adc is active. con5 this bit must be programme d with a logic 0 for correct operation. con4 buf enables the buffer on the analog inputs . if cleared, the analog inputs are unbuffered , lowering the power consumption of the device. if set, the analog inputs are buffered , allowing the user to place sour ce impedances on the front end without contributing gain errors to the system. with the buffer disabled, the voltage on the analog input pins can be from 5 0 mv below a gnd to 5 0 mv above av dd . when the buffer is enabled, it requires some headroom; therefore , the voltage on an y input pin must be limited to 250 mv within the power supply rails. con3 u/ b polarity s elect b it. when this bit is set, unipolar operation is selected. when this bi t is cleared, bipolar operation is selected. c on 2 to con0 g2 to g0 gain s elect b its. written by the user to select the adc input range as follows: g2 g1 g0 gain adc input range (5 v reference , bipolar mode ) 0 0 0 1 5 v 0 0 1 reserved 0 1 0 reserved 0 1 1 8 6 25 mv 1 0 0 16 312. 5 mv 1 0 1 32 156.2 mv 1 1 0 64 78.125 mv 1 1 1 128 39.06 mv
AD7190 data sheet rev. c | page 24 of 40 table 20 . channel selection channel enable bits in the configuration register channel enabled status register bits chd[ 2 :0] calibration register pair ch7 ch 6 ch5 ch4 ch3 ch2 ch1 ch0 positive input ain(+) negative input ain( ?) 1 ain1 ain 2 000 0 1 ain3 ain 4 001 1 1 temperature sensor 010 none 1 ain2 ain 2 011 0 1 ain1 ain com 100 0 1 ain2 ain com 101 1 1 ain3 ain com 110 2 1 ain4 ain com 111 3 data register (rs2, rs1, rs0 = 0, 1, 1; power - on/reset = 0x000000) the conversion result from the adc is stored in this data register. this is a read - only , 24- bit register. on completion of a read operation f rom this register, the rdy pin/bit is set. when the dat_sta bit in the mode register is set to 1, the contents of the status register are appended to each 24 - bit conversion. this is advisable when several analog input channels are en abled because the three lsbs of the status register (chd 2 to chd0) identify the channel from which the conversion originated. id r egister rs2, rs1, rs0 = 1, 0, 0; power - on/reset = 0xx4 the identificat ion number for the AD7190 is stored in the id register . this is a read - only register. gpocon register (rs2, rs1, rs0 = 1, 0, 1; power - on/reset = 0x00) the gpocon register is an 8 - bit register from which data can be read or to which data can be written. this register is used to enable the general - purpose digit al outputs . table 21 outlines the bit designations for the gpocon register. gp0 through gp 7 indicate the bit locations . gp denotes that the bits are in the gpocon register. gp 7 denotes the first bit of the data stream. the num ber in parentheses indicates the power - on/reset default status of that bit.
data sheet AD7190 rev. c | page 25 of 40 gp7 gp6 gp5 gp4 gp3 gp2 gp1 gp0 0(0) bpdsw (0) gp32en (0) gp10en (0) p3dat (0) p2dat (0) p1dat (0) p0dat (0) table 21 . register bit designations bit location bit name description gp7 0 thi s bit must be programmed with a logic 0 for correct operation. gp 6 bpdsw bridge p ower - down switch control b it. this bit is s et by the user to close the bridge power - down switch bpdsw to a gnd. the switch can sink up to 30 ma . the bit is c leared by the user to open the bridge power - down switch. when the adc is placed in power - down mode, the bridge power - down switch remains active. gp5 gp32en digital output p3 and digital output p2 e nable. when gp32en is set, the digital outputs , p3 and p2 , are active. when gp32en is cleared, the p3 and p2 pins are tri stated , and the p3dat and p2dat bits are ignored. gp4 gp10en digital output p1 and digital output p0 e nable. when gp10en is set, the digital outputs , p1 and p0 , are active. when gp10en is cleared , the p1 and p0 outputs are tri stated , and the p1dat and p0dat bits are ignored. the p1 and p0 pins can be used as a reference input refin2 when the refsel bit in the configuration register is set to 1. gp3 p3dat digital output p3. when gp32en is set , the p3dat bit sets the value of the p3 general - purpose output pin. when p3dat is high, the p3 output pin is high. when p3dat is low, the p3 output pin is low. when the gpocon register is read, the p3dat bit reflects the status of the p3 pin if gp32en is set. gp2 p2dat digital output p2. when gp32en is set , the p2dat bit sets the value of the p2 general - purpose output pin. when p2dat is high, the p2 output pin is high. when p2dat is low, the p2 output pin is low. when the gpocon register is read, the p2dat bit reflects the status of the p2 pin if gp32en is set. gp1 p1dat digital output p 1. when gp10en is set , the p1dat bit sets the value of the p1 general - purpose output pin. when p1dat is high, the p1 output pin is hi gh. when p1dat is low, the p1 output pin is low. when the gpocon register is read, the p1dat bit reflects the status of the p1 pin if gp10en is set. gp0 p0dat digital output p0. when gp10en is set , the p0dat bit sets the value of the p0 general - purpose ou tput pin. when p0dat is high, the p0 output pin is high. when p0dat is low, the p0 output pin is low. when the gpocon register is read, the p0dat bit reflects the status of the p0 pin if gp10en is set. o ffset r egister (rs2, rs1, rs0 = 1, 1, 0; power - on/r eset = 0x800000) he oset register holds the oset calibration coeicient or the dc he power - on reset value o the oset register is 0x800000 he d710 has our oset registers ; thereore, each channel has a dedicated oset register each o these registers is a 24 - bit read/write register his register is used in conjunction with its associated ull - scale register to or a register pair he power - on reset value is autoatically overwritten i an internal or syste zero - scale calibration is initiated by the user he d710 ust be placed in power - down ode or idle ode when writing to the oset register full - scale register (rs2, rs1, rs0 = 1, 1, 1; power - on/reset = 0x5xxx x 0) he ull - scale register is a 24 - bit register that holds the u ll- scale calibration coeicient or the dc he d710 has our ull - scale registers ; thereore, each channel has a dedicated ull -scale register he ull - scale registers are read/write registers however, when writing to the ull - scale registers, the dc ust be placed in power - down ode or idle ode hese registers are conigured at power - on with actory - calibrated , ull - scale calibration coe - icients, the calibration being perored at gain = 1 hereore, every device has dierent deault coeicients he deault value is autoatically overwritten i an internal or syste ull - scale calibration is initiated by the user or i the ull - scale register is written to
AD7190 data sheet rev. c | page 26 of 40 adc circuit informat ion mclk1 mclk2 p0/refin2(?) p1/refin2(+) dv dd dgnd 5v ain1 in+ in? out? out+ ain2 ain3 ain4 aincom refin1(?) bpdsw agnd AD7190 refin1(+) reference detect serial interface and control logic temp sensor clock circuitry av dd agnd dout/rdy din sclk cs sync p3 p2 av dd agnd - adc pga mux 07640-012 figure 18 . basic connection d iagram overview the AD7190 is a n ultra low noise adc that incorporates a - ? m odulator, a buffer , pga , and on - chip digital filtering intended for the measurement of wide dynamic range signals such as those in pressure transducers, weigh scales, and strain gauge applications. the part can be configured to have two differential inputs or four pseudo differential inputs that can be buffered or unbuffered. figure 18 shows the basic connections required to operate the part. filter, output data r ate, settling time a -? adc consists of a modulator follow ed by a digital filter. the AD7190 has two filter options: a sinc 3 filter and a sinc 4 filter. the f ilter is selected using the sinc3 bit in the m ode register. when sinc3 is set to 0 (default value), the sinc 4 filter is selected. the sinc 3 filter is selecte d when sinc3 is set to 1. at low output dat a rates (<1 khz), the noise - free resolution is comparable for the two filter types. however, at the higher output dat a rates, the sinc 4 filter gives better noise free resolution. the sinc 4 filter also leads to be tter 50 hz and 60 hz rejection. while the notch positions are not affected by the order of the filter, the higher order filter has wider notches , which leads to better rejection in the band ( 1 hz) around the notches. it also gives better stop - band attenua tion. the benefit of the sinc 3 filter is its lower settling time for the same output data rate. c hop disabled the output data rate (the rate at which conversions are available on a single channel when the adc is continuously converting) is equal to f adc = f clk /(1024 fs [9:0] ) where: f adc is the output data rate. f clk = master clock (4.92 mhz nominal). fs [9:0 ] is the decimal equivalent of b it fs9 to bit fs0 in the m ode register. the output data rate can be programmed from 4.7 hz to 4800 hz; that is, fs [9:0 ] can have a value from 1 to 1023. the previous equation is valid for both the sinc 3 and sinc 4 filters. the settling time for the sinc 4 filter is equal to t settle = 4/ f adc wh ereas the settling time for the sinc 3 filter is equal to t settle = 3/ f adc figure 19 and figure 20 show the frequency response of the sinc 4 and sinc 3 filters , respectively, for an output data rate of 50 hz. 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 25 50 75 100 125 150 filter gain (db) frequency (hz) 07640-013 figure 19 . sinc 4 filter response (50 hz output data rate)
data sheet AD7190 rev. c | page 27 of 40 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 25 50 75 100 125 150 filter gain (db) frequency (hz) 07640-014 figure 20 . sinc 3 filter response (50 hz output data rate) t he sinc 4 filter provides 50 hz ( 1 hz) rejection in excess of 120 db , assuming a stable master clock , while the sinc 3 filter gives a rejection of 100 db. the stop - band attenuation is typically 53 db for the sinc 4 filter but equal to 4 0 db for the sinc 3 filter. the 3 db frequency for the s inc 4 filter i s equal to f 3db = 0.23 f adc and fo r the s inc 3 filter is equal to f 3db = 0.272 f adc c hop enabled wit h chop enab led, the adc offset and offset drift are minimized. when chop is enabled, the analog input pins are continuously swapped. therefore , with the analog input pins connected in one direction, the settling time of the sinc filter is allowed to elapse until a va lid conversion is available. the analog input pins are then inverted and another valid conversion is obtained. subsequent conversions are then averaged so that the offset is minimized. this continuous swapping of the analog input pins and the averaging of subsequent conversions means that the offset drift is also minimized. chopping affects the output data rate and settling time of the adc. for the s inc 4 filter , the output data rate is equal to f adc = f clk /(4 1024 fs [9:0] ) for s inc 3 filter , the output data rate is equal to f adc = f clk /(3 1024 fs [9:0] ) where: f adc is the output data rate. f clk = master clock (4.92 mhz nominal). fs [9:0 ] is the decimal equivalent of b it fs9 to bit fs0 in the mode register. the value of fs [9:0] can be varied from 1 to 1023. this results in an output data rate of 1.173 hz to 1200 hz for the sinc 4 filter and 1.56 hz to 1600 hz for the sinc 3 filter. the settling time for the s inc 3 or s inc 4 filter is equal to t settle = 2/ f adc therefore, with chop enabled, the settling time is reduced for a given output data rate compared to the chop disabled mode. however, for a given fs [9:0] value, the output data rate is less with chop enabled compared with the chop disabled mode. for either the s inc 3 or the s inc 4 filter , the cutoff freq uency f 3db is equal to f 3db = 0.24 f adc figure 21 and figure 22 show the filter response for the sinc 4 and sinc 3 filters , respectively, when chop is enabled. as shown in the plots, the stop - band attenuat ion is less com pared with the chop disabled modes. 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 25 50 75 100 125 150 filter gain (db) frequency (hz) 07640-015 figure 21 . sinc 4 filter response (output d ata r ate = 12.5 hz, chop enabled) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 25 50 75 100 125 150 filter gain (db) frequency (hz) 07640-016 figure 22 . sinc 3 filter response (output d ata rate = 16.6 hz, chop enabled )
AD7190 data sheet rev. c | page 28 of 40 50 hz/ 60 hz rejection normal mode rejection is one of the main functions of the digital filter. with chop disabled, 50 hz rejection is obtained when the output data rate is set to 50 hz , wh ereas 60 hz rejection is achieved when the output data rate is se t to 60 hz. simultaneous 50 hz / 60 hz rejection is obtained when the output data rate is set to 10 hz. simultaneous 50 hz/60 hz rejection can also be achieved using the rej60 bit in the m ode register. when the output data rate is programmed to 50 hz and the rej60 bit is set to 1, notches are placed at both 50 hz and 60 hz . figure 23 and figure 24 show the frequency response of the sinc 4 and sinc 3 filters , respectively, when the output data rate is programm ed to 50 hz and rej60 is set to 1. 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 25 50 75 100 125 150 filter gain (db) frequency (hz) 07640-017 figure 23 . sinc 4 filter response (50 hz output data rate, rej60 = 1) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 25 50 75 100 125 150 filter gain (db) frequency (hz) 07640-018 figure 24 . sinc 3 filter response (50 hz output data rate, rej60 = 1) again, the sinc 4 filter provides better 50 hz/60 hz rejection than the sinc 3 filter. in addition , better stop - band attenuation is achieved with the sinc 4 filter. when chop is enabled, lower output data rates must be used to achieve 50 hz and 60 hz rejection. with rej60 set to 1, a n o utput data rate of 12.5 hz gives simultaneous 50 hz/60 hz rejection when the sinc 4 filter is selected, wh ereas an output data rate of 16.7 hz gives simultaneous 50 hz/ 60 hz rejection when the sinc 3 filter is used. figure 25 and figure 26 show the filter response for both output data rates when rej60 is set to 1 . 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 25 50 75 100 125 150 filter gain (db) frequency (hz) 07640-125 figure 25 . sinc 4 filter response (12.5 hz output data rate, chop enabled, rej60 = 1) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 25 50 75 100 125 150 filter gain (db) frequency (hz) 07640-126 figure 26 . sinc 3 filter response (16.7 hz output data rate, chop enabled, rej60 = 1) zero latency zero latency is enabled by setting the single bit in the mode register to 1. with zero latency, the complete settling time is allowed for each conversion. theref ore, f adc = 1/ t settle zero latency means that the output data rate is constant irrespective of the number of analog input channels enabled; the user does not need to consider the effects of channel changes on the output data rate. the disadvantages of zero latency are the increased noise for a given output data rate compared with the nonzero latency mode. for example, when zero latency is not enabled, the AD7190 has a noise - free resolution of 18.5 bits when the output data rate is 50 hz and the gain is set to 128. when zero latency is enabled, the adc has a resolution of 17.5 bits peak - to - peak when the output data rate is 50 hz. the filter response also changes. figure 19 shows the filter response for the sinc 4 filter when the outpu t data rate is 50 hz (zero latency disabled). figure 27 shows the filter response when zero latency is enabled and the output data rate
data sheet AD7190 rev. c | page 29 of 40 is 50 hz (sinc 4 filter); 50 hz rejection is no longer achieved. the adc needs to operate with an output data rate of 12.5 hz to obtain 50 hz rejection when zero latency is enabled. to obtain simultaneous 50 hz/60 hz rejection, the rej60 bit in the mode register can be set when the output data rate is equal to 12.5 hz. the stop - band attenuation is c onsiderably reduced also (3 db compared with 53 db in the nonzero latency mode). 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 10050 200 300 400 500 150 250 350 450 550 600 filter gain (db) frequency (hz) 07640-020 figure 27 . sinc 4 filter response (50 hz output data rate, zero latency) channel sequencer the AD7190 includes a channel sequencer , which simplifies communic ations with the device in multi channel applic ations. the sequencer also optimizes the channel throughput of the device as the sequencer switches channels at the optimum rate rather than waiting for instructions via the spi interface. bi t s ch0 to bi t ch7 in the c onfiguration register are used to enable the required channels. in continuous conversion mode, the adc select s each of the enabled channels in sequence and perform s a conversion on the channel. the rdy pin goes low when a valid conversion is available on each channel. when several channels are enabled, the contents of the status register should be attached to the 24 - bit word so that the user can identify the channel that corresponds to each conversion. to attach the stat us register value to the conversion, b it dat_sta in the m ode register should be set to 1. when several channels are enabled, the adc must allow the complete settling time to generate a valid conversion each time that the channel is changed. the AD7190 take s care of this : when a channel is selected, the modulator and filter are reset and the rdy pin is taken high. the AD7190 then allows the complete settling time to generate the first conversion. rdy only goes l ow when a valid conversion is available. the AD7190 then selects the next enabled channel and converts on that channel. the user can then read the data register while the adc is performing the conversion on the next channel. the time required to read a val id conversion from all enabled channels is equal to t settle number of enabled channels for example, i f the sinc 4 filter is selected, chop is disabled and zero latency is disabled , conversions are available at 1/f adc when converting on a single channel, w here f adc is equal to the output data rate. the settling time is equal to t settle = 4/f adc the time required to sample n channels is 4/( f adc n ) rdy conversions channel a channel b 1/f adc channel c 07640-019 figure 28 . channel sequencer digital interface as indicated in th e on- chip registers section , the programmable functions of the AD7190 are controlled using a set of on - chip registers. data is written to these registers via the serial interface of the part. r ead access to the on - chip registers is also provided by this interface. all communication with the part must start with a write to the communications register. after power - on or reset, the device expects a write to its communications register. the data written to this register determines whether the next operation is a read operation or a write operation and also de termines which register th is read or write operation affect s. therefore, write access to any of the other registers on the part begins with a write operation to the communications register, follow ed by a write to the selected register. a read operation from any other register (except when continuous read mode is selected) starts with a write to the communications register, followed by a read operation from the selected register. the serial interfa ce of the AD7190 consists of four signals: cs , din, sclk, and dout/ rdy . the din line is used to transfer data into the on - chip registers, wh ereas dout/ rdy is used for accessing data from the on - chip registers. sclk is the serial clock input for the device, and all data transfers (either on din or dout/ rdy ) occur with respect to the sclk signal. the dout/ rdy pin function s as a data ready signa l also, the line going low when a new data - word is available in the output register. it is reset high when a read operation from the data register is complete. it also goes high prior to the updating of the data register to indicate when not to read from t he device, to ensure that a data read is not attempted while the register is being updated. cs is used to select a device. it can be used to decode the AD7190 in systems where several components are connected to the serial bus.
AD7190 data sheet rev. c | page 30 of 40 figure 3 and figure 4 show timing diagrams for interfacing to the AD7190 , with cs being used to decode the part. figure 3 shows the timing for a read operation from the output shift register of the AD7190 , and figure 4 shows the timing for a write operation to the input shift register. it is possible to read the same word from the data register several times even though the dout/ rdy line returns high after the first read operation. however, care must be taken to ensure that the read operations have been com - pleted before the next output update occurs. in continuous read mode, the data register can be re ad only once. the serial interface can operate in 3 - wire mode by tying cs low. in this case, the sclk, din, and dout/ rdy lines are used to communicate with the AD7190 . the end of the conversion can be monitore d using the rdy bit or pin . this scheme is suitable for interfacing to microcontrollers. if cs is required as a decoding signal, it can be generated from a port pin. for microcontroller interfaces, it is recom mended that sclk idle high between data transfers. the AD7190 can be operated with cs used as a frame synchron - ization signal. this scheme is useful for dsp interfaces. in this case, the first bit (msb) is effectively clocked out by cs because cs normally occur s after the falling edge of sclk in dsps. the sclk can continue to run between data transfers, provided the timing numbers are obeyed. the serial interface can be reset by writing a series of 1s to the din input. if a logic 1 is written to the AD7190 din line for at least 40 serial clock cycles, the serial interface is reset. this ensures that the interface can be reset to a known state if the interface gets lost due to a software e rror or some glitch in the system. reset returns the interface to the state in which it is expecting a write to the communications register. this operation resets the contents of all registers to their power - on values. following a reset, the user should allow a period of 500 s before addressing the serial interface. the AD7190 can be configured to continuously convert or to perform a single conversion. see figure 29 through figure 31. single conversio n mode in single conversion mode, the AD7190 is placed in power - d own mode after conversions. when a single conversion is initiated by setting md2, md1, and md0 to 0, 0, 1 , respectively, in the mode register, the AD7190 powers up, performs a single conv ers ion, and then returns to power - down mode. the on - chip oscillator requires 1 ms approximately to power up. dout/ rdy goes low to indicate the completion of a conversion . when the data word has been read from the data register, dout/ rdy go es high. if cs is low, dout/ rdy remain s high until another conversion is initiated and completed. the data register can be read several times, if required, even when dout/ rdy has gone high. if seve ral channels are enabled, the adc sequences through the enabled channels and perform s a conversion on each cha nnel. when a conversion is started , dout/ rdy go es high and remain s high until a valid conversion is available. as soon as the conversion is available, dout/ rdy go es low. the adc then selects the next channel and begins a conversion. the user can read the present conversion while the next conversion is being performed. as soon as the next conversion is complete, the data register is updated ; therefore, the user has a limited period in which to read the conversion. when the adc has performed a single conversion on each of the selected channels, it returns to power - down m ode. if the dat_sta bit in the m ode register is set to 1, the contents of the status register are output along with the conversion each time that the data read is performed. the four lsbs of the status register indi cate the channel to which the conversion corresponds . din sclk dout/rdy cs 0x08 0x58 data 0x280060 07640-021 figure 29 . single conversion
data sheet AD7190 rev. c | page 31 of 40 continuous conversion mode continuous conversion is the default power - up mode. the AD7190 converts continuously , the rdy bit in the status register going low each time a conversion is complete. if cs is low, the dout/ rdy line also goes low when a conversion is completed. to read a conversion, the user writes to the com - munications register, indicating that the next operation is a read of the data register. when the data word has been read from the data register, dout/ rdy go es high. the user can read this register additional times, if required. however, the user must ensure that the data regist er is not being accessed at the completion of the next conversion or else the new conversion word is lost. when several channels are enabled, the adc continuously loop s through the enabled channels, performing one conversion on each channel per loop. the d ata register is updated as soon as each conversion is available. the dout/ rdy pin pulses low each time a conversion is available. the user can then read the conversion while the adc converts on the next enabled channel . if the dat_st a bit in the m ode register is set to 1, the contents of the status register are output along with the conversion each time that the data read is performed. the status register indicates the channel to which the conversion corresponds. din sclk dout/rdy cs 0x58 0x58 data data 07640-022 figure 30 . continuous conversion
AD7190 data sheet rev. c | page 32 of 40 continuous read rather than write to the communications register each time a conversion is complete to access the data, the AD7190 can be configured so that the conversions are placed on the dout/ rdy line automatically. by writing 01011100 to the commun - ications register, the user need only apply the appropriate number of sclk cycles to the adc, and the conversion word is automatically placed on the dout/ rdy line whe n a conversion is complete. the adc should be configured for continuous conversion mode. when dout/ rdy goes low to indicate the end of a conversion, sufficient sclk cycles mu st be applied to the adc ; the data conversion is then plac ed on the dout/ rdy line. when the conversion is read, dout/ rdy returns high until the next conversion is available. in this mode, the data can be read only once. also, the user must ensure that the data - word is read before the next conversion is complete. if the user has not read the conversion before the completion of the next conversion, or if insufficient serial clocks are applied to the AD7190 to read the word, the serial output register is reset when the ne xt conversion is complete and the new conversion is placed in the output serial register. to exit the continuous read mode, the instruction 01011000 must be written to the communications register while the rdy pin is low. while in t he continuous read mode, the adc monitors activity on the din line so that it can receive the instruction to exit the continuous read mode. additionally, a reset occur s if 40 consecutive 1s are seen on din . therefore, din should be held low in continuous r ead mode until an instruction is to be written to the device. when several cha nnels are enabled, the adc continuously step s through the enabled channels and perform s one con - version on each channel each time that it is selected. dout/ rdy pulse s low when a conversion is available. when the user applies sufficient sclk pulses, the data is automatically placed on the dout/ rdy pin. if the dat_sta bit in the m ode register is set to 1, the contents of the status register are output along with the conversion. the status register indicates the channel to which the conversion corresponds. din sclk dout/rdy cs 0x5c data data data 07640-023 figure 31 . continuous read
data sheet AD7190 rev. c | page 33 of 40 circuit description analog input channel the AD7190 has two differential / four pseudo differential analog input channels which can be buffered or unbuffered. in buffer ed mode (the buf bit in the configuration register is set to 1), the input channel feeds into a high impedance input stage of the buffer amplifier. therefore, the input can tolerate significant source impedances and is tailored for direct connection to external resistive - type sensors such as strain gauges or resistance temperature detectors (rtds). when buf = 0, the part is operated in unbuffered mode. this results in a higher analog input current. note that this unbuffered input path provides a dynamic load to the driving source. therefore, resistor/capacitor combinations on the input pins can cause gain errors, depending on the output impedance of the source that is driving the adc input. table 22 shows the allowable external resistance/capacitance values for unbuffered mode at a gain of 1 such that no gain error at the 20 - bit level is introduced. table 22 . external r- c combination for no 20 - bit gain error c (pf) r (?) 50 1.4 k 100 850 500 300 1000 230 5000 30 the absolute input voltage range in buffered mode is restr icted to a range between a gnd + 2 5 0 mv and av dd C 25 0 mv. care must be taken in set ting up the common - mode voltage so that these limits are not exceeded. otherwise, there is degrad ation in linearity and noise performance. the absolute input voltage in unbuffered mode includes the range between a gnd C 5 0 mv and av dd + 5 0 m v. t h e negative absolute input voltage limit does allow the possibility of monitoring small true bipolar signals with respect to a gnd. pga when the gain stage is enabled, the output from the buffer is applied to the input of the programmable gain array (pga) . the presence of the pga means that signals of small amplitude can be gained within the AD7190 while still maintaining excel - lent noise performance. for example, when the gain is set to 128 , the rms noise is 8.5 nv , typically , when the output data rate is 4.7 hz , whi ch is equivalent to 23 bits of effective resolution or 20 .5 bit s of noise - free resolution. the AD7190 can be prog rammed to have a gain of 1 , 8, 16, 32, 64, and 128 using bit g2 to bit g0 in the configuration register. therefore, with an external 2. 5 v ref erence, the un ipolar ranges are from 0 mv to 19.53 mv to 0 v to 2. 5 v , and the bipolar ranges are from 19.53 mv to 2. 5 v. t he analog input range must be limited to (av dd ? 1.25 v)/g ain because the pga require s some headroom. therefore, if av dd = 5 v, t h e maximum analog input that can be ap plied to the AD7190 is 0 to 3.75 v/g ain in unipolar mode or 3.75 v/ g ain in bipolar mode. bipolar/unipolar con figuration the analog input to the AD7190 can accept either unipolar or bipolar input voltage ranges. a bip olar input range does not imply that the part can tolerate negative voltages with respect to system a gnd. in pseudo - differential mode, signals are referenced to aincom while in differential mode, signals are referenced to the negative input of the differe ntial pair. for example, if aincom is 2.5 v and the AD7190 ain1 analog input is configured for unipolar mode with a gain of 2, the input voltage range on the ain 1 pin is 2.5 v to 3.75 v when a 2.5 v reference is used . if aincom is 2.5 v and the AD7190 ain1 analog input is configured for bipolar mode with a gain of 2, the analog input range on ain1 is 1.25 v to 3.75 v. the bipolar/unipolar option is chosen by programming the u/ b bit in the configur ation register. data output coding w hen the adc is configured for unipolar operation, the output code is natural (straight) binary with a zero differential input voltage resulting in a code of 00...00, a midscale voltage result ing in a code of 100...000, and a full - scale input voltage result ing in a code of 111...111. the output code for any analog input voltage can be represented as code = (2 n ain gain )/ v ref when the adc is configured for bipolar operation, the output code is offset binary with a negative full - scale voltage resulting in a code of 000...000, a zero differential input voltage resulting in a code of 100...000, and a positive full - scale input voltage resulting in a code of 111...111. the output code for any analog input voltage can be represented as code = 2 n C 1 [( ain gain / v ref ) + 1] where: ain is the analog input voltage. gain is the pga setting (1 to 128). n = 24 . clock the AD7190 includes an internal 4.92 mhz clock on - chip. this internal clock has a tolerance of 4%. either the internal clock or an external crystal/c lock can be used as the clock source to the AD7190. the clock source is selected using the clk1 and clk0 bits in the mode register. when an external crystal is used, it must be connected across the m c lk1 and m c lk2 pins. the crystal manufacturer recommend s the load capaci - tances required for the crystal. the mclk1 and mclk2 pins of the AD7190 have a capacitance of 15 pf , typically. if an external
AD7190 data sheet rev. c | page 34 of 40 clock source is used, the clock source must be connected to the mclk2 pin and the mclk1 pin must be left floating . the internal clock can also be made available at the mclk2 pin . this is useful when several adcs are used in an application and the devices need to be synchronized. the internal clock from one device can be used as the clock source for all adcs in the system. using a common clock, the devices can be syn - chronized by applying a common reset to all devices , or the sync pin can be pulsed. burnout currents the AD7190 contains two 5 00 na constant current generators, one sourcing curre nt f rom av dd to ain(+) and one sinking current from ain( ?) to a gnd , where ain(+) is the positive analog input terminal and ain( ? ) is the negative analog input terminal in differential mode and aincom in pseudo - differential mode . the currents are switched to the selected analog input pair. both currents are either on or off, depending on the burnout current enable ( burn ) bit in the configuration register. these currents can be used to verify that an external transducer remains operational before attempting t o take measurements on that channel. after the burnout cu rrents are turned on, they flow in the external transducer circuit, and a measurement of the input voltage on the analog input channel can be taken. it will take some time for the burnout currents to detect an open circuit condition as the currents will need to charge any external capacitors there are several reasons why a fault condition can be detected. t he front - end sensor may be open circuit. it could also mean that the front - end sensor is overlo aded , or the reference may be absent and the no ref bit in the status register is set, thus clamping the data to all 1s. t he user needs to check these three cases before making a judgment. if the voltage measured is 0 v, it may indicate that the transducer has short circuited. the current sources work over the normal absolute input voltage range specif ications when the analog inputs are buffered and chop is disabled . reference th e adc has a fully differential input capability for the refer - ence channel. in a ddition, the user has the option of selecting one of two external reference options (refin1(x) or refin2 (x)). the reference source for the AD7190 is selected using the refsel bit in the configuration register. th e refin2 (x) pins are dual purpose: they can function as two general - purpose output pins or as reference pins. when the refsel bit is set to 1, these pins automatically function as reference pins. the common - mode range for these differential inputs is from a gnd to av dd . the reference input is unbuffered; therefore, exces sive r - c source impedances introduce gain errors. the reference voltage refin (refin x (+) ? refin x (?)) is av dd nominal, but the AD7190 is functional with reference voltages from 1 v to av dd . in applications where the excitation (voltage or current) for the transducer on the analog input also drives the reference voltage for the part, the ef fect of the low frequency noise i n the excitation source is remo ved because the application is ratiometric. if the AD7190 is used in a nonratiometric applica - tion, use a lo w noise reference . recommended 2.5 v reference voltage sources for the AD7190 inclu de the adr421 and adr431 , which are low noise references. also note that the reference inputs provide a high impedance, dynamic load. because the input impedance of each reference input is dynamic, resistor/capacitor combinations on these inputs can cause dc gain errors, depending on the output impedance of the source driving the reference inputs. reference voltage sources like those previously recommended (for examp le, adr431 ) typically have low output impedances and are, therefore, tolerant to having decoupling capacitors on refin x (+) without introducing gain errors in the system. deriving the reference input voltage a cr oss an external resistor mean s that the reference input sees a significant external source impedance. external decoupling on the refin x pins is not recommended in this type of circuit configuration. reference detect the AD7190 includes on - chip circuitry to detect whether the part has a valid reference for c onversions or calibrations . this feature is enabled when the ref det bit in the configuration register is set to 1. if the voltage between the selected refin x (+) and refin x(C ) pins is between 0.3 v and 0.6 v, the AD7190 detects that it no longer has a valid reference. in this case, the noref bit of the status register is set to 1. if the AD7190 is performing normal conversions and the noref bit becomes active, the conversion result is all 1s. therefore , it is not necessary to continuous ly monitor the status of the noref bit when performing conversions. it is only necessary to verify its status if the conv ersion result read from the adc data register is all 1s. if the AD7190 is performing eith er an offset or full- scale cali bration and the no ref bit becomes active, the updating of the respective calibration registers is inhibited to avoid loading incorrect coefficients to these registers, and the err bit in the status register is set. if the user is concerned a bout verifying that a valid reference is in place every time a calibration is performed, check the status of the err bit at the end of the calibration cycle. reset the circuitry and serial interface of the AD7190 can be reset by writing consecutive 1s to the device; 40 consecutive 1s are required to perform the reset. this reset s the logic, the digital f ilter, and the analog modulator, wh ereas all on - chip registers are reset to their default values. a reset is a utomatically performed on power - up. when a r eset is initiated, the user must allow a period of 500 s before accessing any of the on - chip registers. a reset is useful if the serial interface loses synchronization due to noise on the sclk line.
data sheet AD7190 rev. c | page 35 of 40 system synchronizati on the sync i nput allows the user to reset the modulator and the digital filter without affecting any of the setup conditions on the part. this allows the user to start gathering samples of the analog input from a known point in time, that is, the rising edge of sync . sync needs to be taken low for four master clock cycles to implement the synchronization function. i f multiple AD7190 devices are operated from a common master clock, they can be synchronized so that their dat a registers are updated simultaneously. a falling edge on the sync pin resets the digital filter and the analog modulator and places the AD7190 into a consistent, known state. while the sync pin is low, the ad7 190 is maintain ed in this state. on the sync rising edge, the modulator and filter are taken out of this reset state and , on the next clock edge, the part starts to gather input samples again. in a system using multiple AD7190 devices, a common signal to their sync pins synchronize s their ope ration. this is normally done after each AD7190 has performed its own calibration or has had calibration coefficients loaded into its calibration registers. the conversions from the AD7190s are then synchronized. the part is taken out of reset on the master clock falling edge following the sync low - to - high transition. therefore, when multiple devices are being synchronized, the sync pin should be taken high on the master clock rising edge to ensure that all devices begin sampling on the master clock falling edge. if the sync pin is not taken high in sufficient time, it is possible to have a difference of one master clock cycle between the devices ; that is, the instant at which c onversions are available differ s from part to part by a maximum of one master clock cycle. the sync pin can also be used as a start conversion command . in this m ode, the rising edge of sync starts conversion , and the falling edge of rdy indicates when the conversion is complete. the disadvantage of this scheme is that the settling time of the filter has to be allowed for each data register update. this means that the rate at which the data register is updated is reduced. for example, if the adc is configured to use the sinc 4 filter, zero latency is disabled and chop is disabled, the data register update takes four times longer. temperature s ensor embedded in the AD7190 is a temperature sensor. this is selected using the ch2 bit in the configuration register. when the ch2 bit is set to 1, the temperature sensor is enabled. when the temperature sensor is selected and bip olar mode is selected, the device should return a code of 0x800000 when the temper - ature is 0 k. a one - poin t calibration is needed to get the optimum performance from the sensor. therefore, a conversion at 25 c should b e recorded and the sensitivity calcul ated . the sensitivit y is ap proximately 2815 codes/c. the equation for the te mperature sensor is temp (k) = ( conversion C 0x800000)/2815 k temp (c) = temp (k) C 273 following the one point calibration, the internal temperature sensor has an accuracy of 2 c , typically. bridge power - down s witch in bridge applications such as strain gauges and load cells, the bridge itself consumes the majority of the current in the system. for example, a 350 load cell require s 15 ma of current when excited with a 5 v supply. to minimize the current consumption of the system, the bridge can be disconnected ( when it is not being used ) using the bridge p ower - down switch . figure 18 shows how the bridge power - down switch is used. the switch can withstand 30 ma of continuous current , and it has an on resistance of 10 maximum. logic o utputs the AD7190 has four general - purpose digit al outputs, p0, p1, p2 , and p3. these are enabled using the gp32en and gp10en bits in the gpocon register. the pins can be pulled high or low using the p0dat to p3dat bits in the gpocon register; that is, the value at the pin is determined by the setting o f the p0dat to p3dat bits . the logic levels for these pins are determined by av dd rather than by dv dd . when the gpocon register is read, the p0dat to p3dat bits reflect the actual value at the pins. this is useful for short - circuit detection. these pins c an be used to drive external circuitry, for example, an external multiplexer. if an external multiplexer is used to increase the channel count, the multiplexer logic pins c an be controlled via the AD7190 general - purpose output pins. the general - purpose out put pins can be used to select the active multiplexer pin. because the operation of the multiplexer is independent of the AD7190, the AD7190 modulator and filter should be reset using the sync pin each time that the multi - plexer chan nel is changed.
AD7190 data sheet rev. c | page 36 of 40 enable parity the AD7190 also has a parity check function on - chip that detects 1 - bit errors in the serial communications between the adc and the microprocessor. when the enpa r bit in the mode register is set to 1 , parity is enabled. the c ontents of the status register must be transmitted along with each 24 - bit conversion when the parity function is enabled. to append the contents of the status register to each conversion read, the dat_sta bit in the mode register should be set to 1 . for ea ch conversion read, the parity bit in the status register is programmed so that the overall number of 1 s transmitted in the 24- bit data - word is even. therefore , for example, if the 24 - bit conversion contains eleven 1 s (binary format) , the parity bit is set to 1 so that the total number of 1s in the serial transmission is even. if the microprocessor receives an odd number of 1 s, it knows that the data received has been corrupted. the parity function only detects 1- bit errors. for example, two bits of corrupt data can result in the microprocessor receiving an even number of 1s. therefore, an error condition is not detected. calibration the AD7190 provides four calibration modes that can be pro - grammed via the mode bits in the mode register. these modes are int ernal zero - scale calibration, internal full - scale calibration, system zero - scale calibration , and system full - scale ca libration . a calibration can be performed at any time b y setting th e md2 to md0 bits in the mode register appropriately. a calibrat ion sho uld be performed when the ga in is changed. after each conversion, the adc conversion result is scaled using the adc calibration registers before being written to the data register. the offset calibration coefficient is subtracted from the result prior to m ultiplication by the full - scale coefficient. to start a calibration, write the relevant value to the md2 to md0 bits . the dout/ rdy pin and the rdy bit in the status register go high when the calibration is init iated. when the calibration is complete , the contents of the corresponding calibration registers are updated, the rdy bit in the stat us register is reset , the dout/ rdy pin returns low (if cs is low), and the AD7190 reverts to idle mode. during an internal zero - scale or full - scale calibration, the res - pective zero input and full - scale input are automatically connected internally to the adc input pins. a system calibration, however, expects the system zero - scale and system full - scale voltages to be applied to the adc pins before initiating the calibration mode. in this way, errors external to the adc are removed. from an operational point of view, treat a calibration like another adc convers ion. a zero - scale calibration, if required, must al ways be performed before a full - scale calibration. set the system software to monitor the rdy bit in the status register or the dout/ rdy pin to determine the e nd of calibration via a polling sequence or an interrupt - driven routine. with chop disabled, both an internal zero - scale calibration and a system zero - scale calibration require a time equal to the settling time, t settle , (4/f adc for the sinc 4 filter and 3/ f adc for the sinc 3 filter). with chop enabled, an internal zero - scale calibration is not needed bec ause the adc itself minimize s the offset continuously . however, if an internal zero - scale ca libration is performed, the settling time, t settle , (2/f adc ) is required to perform the calibra - tion. similarly, a system zero - scale calibration requires a time of t settle to complete. to perform an internal full - scale calibration, a full - scale input voltage is automatically connected to the selected analog input for this calibration. for a gain of 1, the time required for an internal full - scale calibrati on is equal to t settle . for higher gains, the internal full - scale calibration requires a time of 2 t settle . a fu ll- scale calibration is recommended each time the ga in of a channel is changed to minimize the full - scale error. a system full - scale calibration requires a time of t settle . with chop disabled, the zero - scale calibration (internal or system zero - scale ) should be performed before the system full - scale calibra tion is initiated. an in ternal zero -scale calibration , system zero - scale calibration and system full - scale calibration can be performed at any output data rate. an internal full - scale calibration can be performed at any output data ra te for which the filte r word fs[9:0] is divisible by 16, fs[9:0] being the decimal equivalent of the 10 - bit word written to bit fs9 to bit fs0 in the mode register. therefore, internal full - scale calibrations can be performed at output data rates suc h as 10 hz or 50 hz when cho p is disabled . u sing these lower output data rates result s in better calibration accuracy . the offset error is, typically, 100 v/gain. if the gain is changed, it is advisable to perform a calibration. a zero - scale calibration (an internal zero - scale cali bration or system zero - scale calibration) reduces the offset error to the order of the noise. the gain error of the AD7190 is factory calibrated at a gain of 1 with a 5 v power supply at ambient temperature. following this calibration, the gain error is 0 .001% , typically, a t 5 v. table 23 shows the typical un calibrated gain error for the different gain settings. a n internal full- scale calibration reduce s the gain error to 0.001% , typically, when the gain is equal to 1. for higher gains, the gain error post internal full - scale calibration is 0.0075% , typically. a system full - sale calibration reduces the gain error to the order of the noise. table 23. typical precalibration gain error vs. gain gain precalibrat ion gain error (%) 8 ?0.11 16 ?0.20 32 ?0.23 64 ?0.29 128 ?0.39
data sheet AD7190 rev. c | page 37 of 40 the AD7190 gives the user access to the on - chip calibration registers, allowing the microprocessor to read the calibration coefficients of the device and also to write its own ca libration coefficients from pr e stored values in the eeprom. a read of the registers can be performed at any time. however, the adc must be placed in power - down or idle mode when writing to the registers. the values in the calibration registers are 24 - bits wide. the span and offset of t he part can also be manipulated using the registers. grounding and layout because the analog inputs and reference inputs are differential, most of the voltages in the analog modulator are comm on - mode voltages. the high c ommon - mode rejection of the part remove s common - mode noise on these inputs. the analog and digit al supplies to the AD7190 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. the digital filter provide s rejection of broadband n oise on the power supplies, except at integer multiples of the modulator sampling frequency. connect an r - c filter to each analog input pin to p rovide rejection at the modulator sampling frequency. a 100 ? resistor in series with each analog input , a 0.1 f capacitor between the analog inputs along with a 0.01 f capacitor from each analog input to agnd is advised. the digital filter also removes noise from the analog and reference inputs provided these no ise sources do not saturate the analog modulator. as a result, the AD7190 is more immune to noise interference than a conventional high resolution converter. however, because the resolution of the AD7190 is so high and the noise levels from the converter s o low, care must be taken with regard to grounding and layout. the printed circuit board (pcb) that houses the adc m us t be designed so that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use o f ground planes that can be easily separated. a minimum etch technique is generally best for ground planes because it gives the best shielding. although the AD7190 has separate pins for analog and digital ground, the agnd and dgnd pins are tied together in ternally via the substrate. therefore, the user must not tie these two pins to separate ground planes unless the ground planes are connected together near the AD7190. in systems in whic h the agnd and dgnd are connected somewhere else in the system (that is, the power supply of the system) , they should not be connected again at the AD7190 because a ground loop result s . in these situations , it is recommended that ground pins of the AD7190 be tied to the agnd plane. in any layout , the user must keep in mind th e flow of currents in the system, ensuring that the paths for all currents are as close as possible to the paths the currents took to reach their destin - ations. avoid forcing digital currents to flow through the agnd. avoid running digital lines under the device because this couple s noise onto the die and allow t he analog ground plane to run under the AD7190 to prevent noise coupling. the power supply lines to the AD7190 must use as wide a trace as possible to provide low impedance paths and reduce the effe cts of glitches on the power supply line. shield f ast switching signals like clocks with digital ground to prevent radiating noise to other sections of the board , and never run clock signals near the analog inputs. avoid crossover of digital and analog sig nals. run t races on opposite sides of the board at right angles to each other. this reduce s the effects of feedthrough through the board. a microstrip technique is by far the best but is not always possible with a double - sided board. in this technique, the component side of the boar d is dedicated to ground planes, whereas signals are placed on the solder side. good decoupling is important when using high resolution adcs . decouple a ll analog supplies with 10 f tantalum in parallel with 0.1 f capacitors to agnd. to achieve the best from these dec oupling components, place them as close as possible to the device, ideally right up against the device. decouple a ll logic chips with 0.1 f ceramic capacitors to dgn d. in systems in which a common supply voltage is used to drive both the a v dd and dv dd of the AD7190, it is recommended that the system av dd s upply be used. for t his supply , place the recommended analog supply decoupling capacitors between the av dd pin of the AD7190 and agnd and the recommended digital supply decoupling capacitor between the dv dd pin of the AD7190 and dgnd.
AD7190 data sheet rev. c | page 38 of 40 applications information the AD7190 provides a low - cost, high resolution analog - to - digital function. because the analog - to - digital f unction is provided by a - ? architecture, it makes the part more immune to noisy environments, making it ideal for use in sensor measurement and industrial and process control applications. w eigh s cales figure 32 sho ws the AD7190 being used in a weigh scale application. the load cell is arranged in a bridge network and gives a differential output voltage between its out+ and out C terminals. assuming a 5 v excitation voltage, the full - scale output range from the transducer is 10 mv when the sensitivity is 2 mv/v. the excitation voltage for the bridge can be used to directly provide the reference for the adc because the reference input ran ge includes the supply voltage. a second advantage of using the AD7190 in transducer - base d applications is that the bridge power - down switch can be fully utilized to minimize the power consumption of the system. the bridge power - down switch is connected in series with the cold side of the bridge. in normal operation, the switch is closed and m easurements can be taken. in applications in which current consumption is being minimized, the AD7190 can be placed in standby mode, thus significantly reducing the power consumed in the application. in addition, the bridge power - down switch can be opened while in standby mode, thus avoiding unnecessary power consumption by the front - end transducer. when the part is taken out of standby mode and the bridge power - down switch is closed, the user should ensure that the front - end circuitry is fully settled befo re attempting a read from the AD7190. for simplicity, external filte rs are not included in figure 32. however, an r - c anti alias filter should be included on each analog input. this is require d because the on - chip digital filte r does not provide any rejection around the modulator sampling frequency or multiples of this frequency. suitable values are a 100 resistor in series with each analog input, a 0.1 f capa - citor between the analog inputs and 0.01 f capacitors from each analog input pin to agnd. mclk1 mclk2 p0/refin2(?) p1/refin2(+) dv dd dgnd 5v ain1 in+ in? out? out+ ain2 ain3 ain4 aincom refin1(?) bpdsw agnd AD7190 refin1(+) reference detect serial interface and control logic temp sensor clock circuitry av dd agnd dout/rdy din sclk cs sync p3 p2 av dd agnd - adc pga mux 07640-024 figure 32 . typical application (w eig h s cale )
data sheet AD7190 rev. c | page 39 of 40 outline dimensions 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane 0.10 coplanarity compliant to jedec standards mo-153-ad figure 33 . 24 - lead thin shrink small outline package [tssop] (ru - 24) dimensions shown in millimeters ordering guide models 1 , 2 temperature range package description package option AD7190 bruz C 40c to +105c 24- lead tssop ru -24 AD7190 bruz - reel C 40c to +105c 24- lead tssop ru -24 AD7190wbruz C 40c to +105c 24- lead tssop ru -24 AD7190wbruz - rl C 40c to +105c 24- lead tssop ru -24 eval - AD7190ebz evaluation board 1 z = rohs compliant part. 2 w = qualified for automotive applications . automotive products the ad 7190 w models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. note that these automot ive models may have specifications that differ from the commercial models; therefore, designers should review the specifications section of this data sheet carefully. only the automotive grade products shown are available for use in automotive applications. contact your local analog devices account representative for specific product ordering information a nd to obtain the specific automotive reliability reports for these models.
AD7190 data sheet rev. c | page 40 of 40 ?2008C2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07640-0-2/13(c) notes

▲Up To Search▲

Price & Availability of AD7190

	To Download AD7190 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .